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Planar Engineering for Type-II Superlattices (PETS

Award Information
Agency: Department of Defense
Branch: Army
Contract: W15P7T-10-C-S205
Agency Tracking Number: A092-080-0150
Amount: $69,968.00
Phase: Phase I
Program: SBIR
Solicitation Topic Code: A09-080
Solicitation Number: 2009.2
Timeline
Solicitation Year: 2009
Award Year: 2009
Award Start Date (Proposal Award Date): 2010-02-22
Award End Date (Contract End Date): 2010-08-22
Small Business Information
1801 Maple Avenue
Evanston, IL 60201
United States
DUNS: 129503988
HUBZone Owned: No
Woman Owned: No
Socially and Economically Disadvantaged: No
Principal Investigator
 Ryan McClintock
 Technical Director
 (847) 491-7208
 rmcclin@gmail.com
Business Contact
 Manijeh Razeghi
Title: President
Phone: (847) 491-7208
Email: razeghi@eecs.northwestern.edu
Research Institution
N/A
Abstract

Type II InAs/GaSb strained layer superlattices (SLS) represent the most promising material system capable of delivering more producible, large-format MWIR and LWIR focal plane arrays (FPAs). Type-II SLS currently achieve performance comparable to that of existing mercury-cadmium-telluride (MCT) based FPAs. However, no viable planar processing techniques have been demonstrated for Type-II ¡V they currently rely on mesa isolated diodes. These mesas require etching, cleaning, and passivation, which complicate the processing of Type-II SLS and can decrease the yield and reliability. As such it is desirable to pursue a planar processing technique that is compatible with Type-II superlattices. In this proposal we present a novel planar design compatible with Type-II design called Planar Engineering for Type-II Superlatices (PETS). PETS consists of a reduced area p-type GaSb layer that is fabricated via selective area re-growth in a trench in a ƒÞ-type (lightly n-type) absorbing layer. This eliminates the need to passivate the devices and simplifies the processing, and thus can be expected to increase the yield and reliability leading to a more producible FPA. In addition PETS allows for a reduced junction area while maintaining the optical area of the device. This will reduce the dark current and lead to higher signal to noise ratios.

* Information listed above is at the time of submission. *

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