FPGA Low Power Design Rules

Award Information
Agency:
Department of Defense
Branch
Army
Amount:
$69,993.00
Award Year:
2010
Program:
SBIR
Phase:
Phase I
Contract:
W31P4Q-10-C-0183
Agency Tracking Number:
A093-127-1197
Solicitation Year:
2009
Solicitation Topic Code:
A09-127
Solicitation Number:
2009.3
Small Business Information
BINACHIP, INC.
203 N. WABASH AV, SUITE 203, CHICAGO, IL, 60601
Hubzone Owned:
N
Socially and Economically Disadvantaged:
N
Woman Owned:
N
Duns:
134656532
Principal Investigator:
David Zaretsky
Chief Executive Officer
(312) 346-5660
david@binachip.com
Business Contact:
Prith Banerjee
Chairman, Chief Technical Officer
(847) 757-8708
mcannon@knology.net
Research Institution:
n/a
Abstract
Commercial FPGA programming software tools use logic synthesis tools to route the connections between logic gates, look-up tables, and memory units. Current commercial tools, however, are optimized to maximize operation speed and minimize area and memory utilization. This proposal addresses the needs of the Department of Defense for a solution that provides a means of reducing FPGA power consumption for any specific target architecture. We proposed in this Phase I research to develop the LPS (Low-Power Synthesis) tool, a stand-alone software tool plugin for commercial synthesis tools that will optimize RTL designs for low-power. The LPS tool will take in an input RTL design and a set of design rules for the target FPGA architecture, perform a comprehensive set of low-power optimizations, and then generate an output RTL design for the backend logic synthesis tool. We will test the power optimizations and the LPS tool on a set of large multi-media benchmarks. Our proposed work will address DOD’s requirements for a low-power synthesis tool by providing a generic entry point for virtually all commercial logic synthesis tools, providing a low-cost solution for low-power FPGA design, and providing an automated framework that will reduce low-power design times from months to hours.

* information listed above is at the time of submission.

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