Self-Assembly Production of Hybrid CMOS/Nanodevice Interconnects
Department of Defense
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Small Business Information
P.O. Box 618, Christiansburg, VA, 24068
Socially and Economically Disadvantaged:
AbstractThe objective of the proposed SBIR program is to develop wet chemistry nanopatterning techniques compatible with conventional IC gate array processing materials and methods, and capable of fabricating conducting nanorod geometries to address individual elements in dense arrays. NanoSonic and the deep UV photolithography laboratory at Virginia Tech would cooperate on this program. NanoSonic would use its molecular-level self-assembly process with Virginia Tech’s holographic interference-based DUV lithography designs to produce multilayered interconnected nanowire/nanofin structures on silicon substrates. Prior cooperative work has demonstrated the feasibility of forming electrically conductive pin/post arrays in 2D square and hex geometries with 50nm periodicity, and single layer nanowire/nanofin arrays of similar conducting materials with comparable sub-100nm periods. During Phase I, we would demonstrate that wet chemistry self-assembly and stand-off interference lithography may be used to form skewed crossed-nanorod interconnect arrays to address individual nano-sized MOSFET gate elements in large 2D formats. Such interconnects are key enablers for molecular topologies for next-generation, ultra-high density CMOS logic and memories. NanoSonic would work closely with a major defense contractor and specialized IC manufacturer during Phase I to evaluate manufactured prototypes, and would work with that company to transition developed technology to their production facility during Phase II.
* information listed above is at the time of submission.