High Density Shock Survivable Microelectronics
Small Business Information
11409 Valley View Road, Eden Prairie, MN, 55344
Robert A. Sinclair
AbstractA packaging system and process for minimizing the volume of shock hardened components will be designed and developed. Different multi-chip module (MCM) approaches will be investigated including laminate (MCM-L), ceramic (MCM-C), deposited thin film (MCM-D), and hybrids of the two (MCM-C/D). In addition, micro ball grid arrays on folded elastomeric substrates, 3-D High Density Interconnect (HDI) technology, and Stacked Silicon (SS) technologies will be evaluated. Samples of the selected technology will be tested with NVE's High G Tester (HGT) to prove their survivability. Increasing density by combining functions for a typical data recorder application on a single die will also be investigated such as incorporating a 32K x 8 high speed non-volatile memory, an analog-to-digital converter, and microprocessor on the same die using NVE's integrated circuit design technology. This chip could then be incorporated with the technology selected into an ultra dense stacked 3-D multichip module. NVE's new Magnetoresistive Random Access Memory (MRAM) technology would be studied for use in the 32K x 8 nonvolatile memory by shock testing arrays to insure that the bit designs were immune to magnetostriction. The results of this study would lead to an ultra-dense, high shock, programmable data recorder during a Phase II effort.
* information listed above is at the time of submission.