Integrated Spin Dependent Hot-Electron Transistor

Award Information
Agency: Department of Defense
Branch: Missile Defense Agency
Contract: N/A
Agency Tracking Number: 35841
Amount: $59,998.00
Phase: Phase I
Program: SBIR
Awards Year: 1997
Solicitation Year: N/A
Solicitation Topic Code: N/A
Solicitation Number: N/A
Small Business Information
11409 Valley View Rd., Eden Prairie, MN, 55344
HUBZone Owned: N
Woman Owned: N
Socially and Economically Disadvantaged: N
Principal Investigator
 Mark Tondra
 (612) 996-1615
Business Contact
Phone: () -
Research Institution
The objective of this Phase I project is to demonstrate, using a process compatible with mass production, a new type of magnetic metal-base transistor by combining the giant magnetoresistance (GMR) effect with semiconductor technology. The resulting transistor device will have the potential to be radiation hard, and very high speed, both of which are beneficial for military and space applications. Creation of this device will require progress in two main areas: application of cutting edge lithographic processes to GMR materials, and the construction of a GMR metal - semiconductor interface. Pioneering work in this area by Monsma, et. al., has shown an almost 400% change in collector current with the application of a magnetic field in similar structure. While those results were obtained at low temperature and in relatively high fields, the process proposed here should achieve similar results at room temperature in minimal fields due to the use of high resolution lithography and better GMR materials. Once the basic transistor properties are verified, a Phase II program will optimize the device properties, explore integration with other circuits, improve the producibility of the devices, and investigate likely advantages such as radiation hardness. Integrating GMR materials with semiconductor transistors will result in greatly improved the density (lower cost) for MRAM, a ten-fold increase in the sensitivity of low magnetic field sensors, and potentially a rad-hard logic family.

* Information listed above is at the time of submission. *

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