Securely configurable gate arrays utilizing anti-tamper memory

Award Information
Agency: Department of Defense
Branch: Missile Defense Agency
Contract: HQ0006-06-C-7520
Agency Tracking Number: B064-008-0077
Amount: $99,998.00
Phase: Phase I
Program: STTR
Awards Year: 2006
Solicitation Year: 2006
Solicitation Topic Code: MDA06-T008
Solicitation Number: N/A
Small Business Information
11409 Valley View Road, Eden Prairie, MN, 55344
DUNS: 114264351
HUBZone Owned: N
Woman Owned: N
Socially and Economically Disadvantaged: N
Principal Investigator
 James Deak
 Senior Physicist
 (952) 996-1636
 jdeak@nve.com
Business Contact
 Richard George
Title: Director Government Contract Adm.
Phone: (952) 996-1602
Email: dickg@nve.com
Research Institution
 OREGON STATE UNIV.
 Albrecht Jander
 School of EE and CS Rm. 1148 K
Corvallis, OR, 97331
 (541) 737-2974
 Nonprofit college or university
Abstract
This Small Business Technology Transfer Phase I project proposal describes a program to develop secure FPGA architectures and configuration algorithms that exploit the unique capabilities of a new anti-tamper memory technology called AT-MRAM, that provides strong protection against invasive attacks used to recover the intellectual property stored in the FPGA configuration. AT-MRAM provides protective layers, that when breached cause the data stored in the memory to be erased with no remanence. The erasure mechanism does not require applied power. The AT-MRAM protective layers also function as electromagnetic shielding, providing immunity to EM-based side-channel attacks. In addition, AT-MRAM is intrinsically radiation hard. There is not a single secure FPGA available today with an unpowered zero-remanence erasure feature that is triggered by removal of shielding layers. This unique capability will greatly enhance FPGA security.

* Information listed above is at the time of submission. *

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