Multi-processor Embedded Front-End Electronics Platform with Multi-Function Network for Pulsed Accelerator Control Systems

Award Information
Agency: Department of Energy
Branch: N/A
Contract: DE-FG02-05ER84366
Agency Tracking Number: 78911S05-I
Amount: $99,996.00
Phase: Phase I
Program: SBIR
Awards Year: 2005
Solicitation Year: 2006
Solicitation Topic Code: 36
Solicitation Number: DE-FG02-06ER06-09
Small Business Information
18 Meudon Drive, Locust Valley, NY, 11560
HUBZone Owned: N
Woman Owned: N
Socially and Economically Disadvantaged: N
Principal Investigator
 Eric Siskind
 (516) 759-0707
Business Contact
 Eric Siskind
Title: Dr.
Phone: (516) 759-0707
Research Institution
78911S Electronics for pulsed front-end devices at pulsed particle accelerators are typically accessed through up to 4 networks, which carry timing information, pulse-to-pulse sequencing, real-time streaming data, and configuration information, respectively. Although modern commercial networks offer a rich variety of features, they are not well optimized to the needs of pulsed accelerators for clocking, pulse-by-pulse control, or reliable real-time data acquisition with sub-millisecond timeouts in an electrically noisy environment. In this project, circuit switching will be used to provide preferential delivery of real-time data streams, with error correction adding noise immunity. The accelerator clock frequency will be carried by synchronizing the data link byte clock to the accelerator clock. Clock phase and fiducial timing data will be sent by custom extensions to the circuit switching protocols. Separate embedded power PC processors coupled via shared memory within a single field programmable gate array (FPGA) will be employed for real-time and non-real-time functions. Phase I will extend a previously developed approach for circuit switching both real-time and non-real-time data onto a single network physical link to carry accelerator clock and fiducial timing data. An additional technology for coupling multiple power PC processors, embedded within a single FPGA via shared memory, also will be developed. Both technologies will be combined with a dual-access PCI (Peripheral Component Interconnect) master, in an FPGA design intended for use, on a demonstration hardware platform packaged as a PCI mezzanine card. Commercial Applications and Other Benefits as described by the awardee: The technology should find application in computer network interface cards, network fabric switching points, and embedded device controllers for accelerator devices. The use of such techniques should lead to more reliable accelerators.

* Information listed above is at the time of submission. *

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