INTELLIGENT BUFFER FOR ON-LINE REAL-TIME COMPENSATION OF ARRAY DISTORTIONS

Award Information
Agency:
Department of Defense
Branch
Navy
Amount:
$53,645.00
Award Year:
1987
Program:
SBIR
Phase:
Phase I
Contract:
n/a
Award Id:
6202
Agency Tracking Number:
6202
Solicitation Year:
n/a
Solicitation Topic Code:
n/a
Solicitation Number:
n/a
Small Business Information
145 Palisade St, Dobbs Ferry, NY, 10522
Hubzone Owned:
N
Minority Owned:
N
Woman Owned:
N
Duns:
n/a
Principal Investigator:
ROSS E WILLIAMS
(914) 693-9001
Business Contact:
() -
Research Institution:
n/a
Abstract
A DESIGN APPROACH USING HIGH SPEED MICROPROCESSORS AND RAPID-ACCESS MEMORY DEVICES IS SUGGESTED FOR A STAND-ALONE INTELLIGENT BUFFER THAT INSERTS DELAYS TO COMPENSATE FOR SENSOR POSITION ERRORS IN THE SENSOR DATA STREAM THAT FEEDS A CONVENTIONAL BEAMFORMER IN REAL-TIME. THE MOTOROLA 68020 AND INTEL 80386 32 BIT HIGH SPEED MICROPROCESSOR CHIPS HAVE SEVERAL ATTRACTIVE FEATURES FOR THIS APPLICATION WHEN USED TO CONTROL THE INSERTION AND REMOVAL OF SERIAL SENSOR DATA IN FIFO FASHION FROM VERY FAST RANDOM OR SERIAL ACCESS MEMORY CHIPS. A BLOCK DIAGRAM IS GIVEN FOR THE SYSTEM CONCEPT. A HYPOTHETICAL ARRAY EXAMPLE IS PRESENTED TO ILLUSTRATE DATA RATES, PROCESSING LOAD, AND REAL-TIME CAPABILITY. IN PHASE I, OAS WILL DETERMINE MAXIMUM DELAYS REQUIRED FOR COMPENSATION AND THE NUMBER OF ANGULAR SECTIONS TO BE COMPENSATED. HARDWARE DESIGN ALTERNATIVES WILL BE EVALUATED AND OPTIMUM COMPONENTS SPECIFIED. A TIMING SEQUENCE WILL BE ESTABLISHED FOR ON-LINE OPERATIONS, AND A FLOW DIAGRAM FOR MICROPROCESSOR SOFTWARE WILL BE DEFINED.

* information listed above is at the time of submission.

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