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FPGA Hardening Against Vulnerabilities and Radiation Effects

Award Information
Agency: Department of Defense
Branch: Navy
Contract: N64267-23-C-0028
Agency Tracking Number: N231-073-0321
Amount: $146,406.00
Phase: Phase I
Program: SBIR
Solicitation Topic Code: N231-073
Solicitation Number: 23.1
Solicitation Year: 2023
Award Year: 2023
Award Start Date (Proposal Award Date): 2023-07-18
Award End Date (Contract End Date): 2024-01-15
Small Business Information
531 Esty Street
Ithaca, NY 14850-3250
United States
DUNS: 603978321
HUBZone Owned: No
Woman Owned: No
Socially and Economically Disadvantaged: No
Principal Investigator
 Jason Dickens
 (607) 273-7340
Business Contact
 Daniel Goodwin
Phone: (410) 952-9439
Research Institution

Field-programmable gate arrays (FPGAs) are becoming increasingly important components in advanced electronics systems. FPGA devices can provide significant design flexibility, performance, and reconfigurability. However, these devices do not currently meet the goals for strategic systems assurance, which limits their use in these applications. These systems operate in environments where radiation effects must be both minimized and mitigated. Assurances are needed that these systems can recover from various single event effects and cumulative effects induced by radiation sources as well as ensure that the designs as implemented do not contain bugs or Trojans. GrammaTech is proposing to leverage its existing FPGA silicon and FPGA design analysis technologies to both detect vulnerability in FPGAs as well as to monitor, and mitigate radiation effects in an innovative new way, while also involving traditional approaches. By research the new approach and developing automation tools we will develop FPGA architecture changes that could be incorporated into future FPGA architectures to build in these assurances. This research will augment our exiting FPGA assurance tools with the capabilities to automatically monitor and mitigate for radiation applications. Subsequent research would involve support the developed technology natively with the FPGA silicon design.

* Information listed above is at the time of submission. *

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