MONOLITHIC OPTICS FOR HIGHLY PARALLEL OPTICAL BACKPLANE

Award Information
Agency:
Department of Defense
Branch
Air Force
Amount:
$99,999.00
Award Year:
1998
Program:
SBIR
Phase:
Phase I
Contract:
n/a
Award Id:
40949
Agency Tracking Number:
40949
Solicitation Year:
n/a
Solicitation Topic Code:
n/a
Solicitation Number:
n/a
Small Business Information
3450 HILLVIEW AVENUE, Palo Alto, CA, 94304
Hubzone Owned:
N
Minority Owned:
N
Woman Owned:
N
Duns:
n/a
Principal Investigator:
Dr Matthew Derstine
(650) 855-1776
Business Contact:
() -
Research Institute:
n/a
Abstract
Emerging weapon system's need for high performance processor with large addressable memory will continue to increase, Airborne systems (e.g. Joint STARS, JSF, and AWACS) will have processing needs approaching Tera-ops packaged in a single chasis and rack. Continued evolution of digital CMOS technology processors can provide the basis for supporting these requirements; Giga-op single chip processing devices will be available in the near future. However this increase in processing power will not necessarily result in higher performance embedded military processing systems. This is because the electrical interconnect fabric is not scaleable with digital signal processing technology. This proposal describes a plan to develop key optical elements for a parallel optical backplane system that will address this interconnection bottleneck. We propose the use of injection molding to create a monolithic optical assembly with precise mounting fixtures will reduce the cost of the fabrication, assembly and maintenance on the modules used to implement the backpalne. During the Phase I we will define, design, fabricate and test the optical component. The performance objective for the part are >1000 interconnects per centimeter of board edge. In Phase II this element will be integrated with the VCSEL-based optoelectronics.

* information listed above is at the time of submission.

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