Phase-Only Piston Microelectromechanicla Spatial Light Modulator

Award Information
Agency:
Department of Defense
Branch
Office of the Secretary of Defense
Amount:
$80,083.00
Award Year:
1999
Program:
SBIR
Phase:
Phase I
Contract:
992WMN331
Award Id:
44796
Agency Tracking Number:
992WMN331
Solicitation Year:
n/a
Solicitation Topic Code:
n/a
Solicitation Number:
n/a
Small Business Information
3 Preston Court, Bedford, MN, 01730
Hubzone Owned:
N
Minority Owned:
N
Woman Owned:
N
Duns:
n/a
Principal Investigator:
Vernon Shrauger
(781) 275-3100
Business Contact:
() -
Research Institution:
n/a
Abstract
Not Available This Small Business Innovation Research Phase I project demonstrates a breakthrough approach to very high-speed, high-resolution A/D conversion which improves the speed by up to six times the state-of-the-art by using a parallel array of individual converters. The significant performance improvements afforded by the Advanced Filter Bank Analog-to-Digital Converter (AFB ADC) architecture will be demonstrated in Phase I by building and testing a pre-prototype breadboard implementation of the front-end electronics of a 14-bit AFB ADC system with 260 MHz sample rate (four times the speed of state-of-the-art). A faster, single chip 14-bit AFB ADC with 390 MHz sample rate will be developed in Phase II. V Company and Raytheon E-Systems in Falls Church, VA have formed a strategic alliance to collaborate on this project. The architecture works because the filter bank signal processing significantly reduces the sensitivity to analog mismatches (e.g., phase distortion, clock skew, temperature drift) which prohibit existing parallel conversion methods (e.g., Time-Interleaving) from achieving high resolution. V Company has proven the technical efficacy of the concept by successfully building and testing breadboard circuitry with 12-bit resolution and 80 MHz sample rate. The AFB ADC architecture will always exceed the state-of-the-art because it can easily be upgraded as new, more powerful ADC products become available. The architecture is amenable to single-chip integration for compact, low-power applications.

* information listed above is at the time of submission.

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