Design Tools for Integrated Asynchronous Electronic Circuits

Award Information
Agency:
Department of Defense
Branch
Defense Advanced Research Projects Agency
Amount:
$99,000.00
Award Year:
2002
Program:
SBIR
Phase:
Phase I
Contract:
DAAH0103CR016
Award Id:
58453
Agency Tracking Number:
02SB2-0325
Solicitation Year:
n/a
Solicitation Topic Code:
n/a
Solicitation Number:
n/a
Small Business Information
17371 NE 67th Court, Suite 205, Redmond, WA, 98052
Hubzone Owned:
N
Minority Owned:
N
Woman Owned:
N
Duns:
010947088
Principal Investigator:
MonteMar
Chief Scientist
(425) 702-9196
monte.mar@orora.com
Business Contact:
TraceyLuo
VP Business Operation
(425) 702-9196
tracey.luo@orora.com
Research Institute:
n/a
Abstract
"Asynchronous circuit design has the potential to offer orders of magnitude improvement in speed, power dissipation and EMI over synchronous circuit design. It is especially appealing to military electronics due to its extremely low EMI performance and itssuitability as an enabling technology for heterogeneous system integration with high reliability and affordability. However, its real silicon success has been extremely limited due to lack of supporting CAD tools. In this SBIR project, we propose todevelop CASTER (CMOS Asynchronous System Timing, Energy and Radiation): a CAD tool for silicon-accurate analysis and optimization of timing, power and EMI of asynchronous circuits. CASTER partitions a transistor-level asynchronous circuit into a graph oftransistor-channel-connected blocks (TCCB) communicating through asynchronous handshaking signals. Each TCCB can be modeled in the same way as in a synchronous CMOS circuit, and can be analyzed by using parasitic-aware behavioral modeling from DARPANeoCAD. We propose to study the feasibility of using CASTER for asynchronous performance metric study and design methodology evaluation. Further, we propose to demonstrate coupled optimization of asynchronous circuit density, speed, power and EMI noise byusing CASTER to incorporate physical design and layout parameters, and then use our ARSYN optimizer for architecture exploration. The proposed CAD tools CASTER/ARSYN can reduce the design cycle t

* information listed above is at the time of submission.

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