CAD Tools for 3-Dimensional VLSI Circuits

Award Information
Agency: Department of Defense
Branch: Defense Advanced Research Projects Agency
Contract: DAAH0102CR137
Agency Tracking Number: 02SB1-0264
Amount: $98,893.00
Phase: Phase I
Program: SBIR
Awards Year: 2002
Solitcitation Year: N/A
Solitcitation Topic Code: N/A
Solitcitation Number: N/A
Small Business Information
Orora Design Technologies, Inc.
17371 NE 67th Court, Suite 205, Redmond, WA, 98052
Duns: 132082277
Hubzone Owned: N
Woman Owned: N
Socially and Economically Disadvantaged: N
Principal Investigator
 Monte Mar
 Chief Scientist
 (425) 702-9196
 monte.mar@orora.com
Business Contact
 Tracey Luo
Title: Business Manager
Phone: (425) 702-9196
Email: tracey.luo@orora.com
Research Institution
N/A
Abstract
"Three dimensional integration offers the potential of orders of magnitudeimprovement by reducing interconnect lengths and delays. With recent breakthroughsin manufacturing technology, 3-D circuits are emerging as a commercially viablesolution to enable continued technology development conforming to Moore's Law.However, the exploration of 3-D circuits will be hampered by a lack of designtools for thermal investigation and 3-D place and route. In this SBIR proposal,Orora Design Technologies (ODT) proposes the development of a new generation ofCAD tools and a design methodology for three-dimensional integrated circuits.ODT will develop a VHDL-AMS based methodology will be developed and demonstratedfor modeling and simulation of the coupled electrical and thermal performances of3-D circuits. Innovative place-and-route tools will be developed to facilitateexploration and multi-objective optimization of 3-D circuits. The design of anasynchronous FFT processor tailored to the 3-D structure will be chosen to allowdemonstration of performance gains in reducing latency, increasing clock speed,and increasing density while still maintaining reasonable power dissipation. Three dimensional integration hold the potential for increasing circuit performance.By stacking circuits, an increase in circuit density and a decrease in the lengthof critical routes can be achieved. This in turn will alleviate the burdens placedon the large die currently implem

* information listed above is at the time of submission.

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