VECTOR PROCESSORS FOR SYSTOLIC ARRAYS

Award Information
Agency: National Science Foundation
Branch: N/A
Contract: N/A
Agency Tracking Number: 10693
Amount: $50,000.00
Phase: Phase I
Program: SBIR
Awards Year: 1989
Solicitation Year: N/A
Solicitation Topic Code: N/A
Solicitation Number: N/A
Small Business Information
3424 Nw 31st St, Gainesville, FL, 32605
DUNS: N/A
HUBZone Owned: N
Woman Owned: N
Socially and Economically Disadvantaged: N
Principal Investigator
 Michael F Griffin
 Principal Investigator
 (904) 371-2567
Business Contact
Phone: () -
Research Institution
N/A
Abstract
THE DIGITAL SIGNAL AND IMAGE PROCESSING INDUSTRY CONTINUES TO ENJOY PHENOMENAL GROWTH. HOWEVER, MANY COMPUTER-BOUND, HIGH-END, REAL-TIME NEEDS ARE NOT CURRENTLY BEING MET. APPLICATION AREAS TYPIFYING THESE REQUIREMENTS ARE COMMUNICATIONS, RADAR/SONAR, SPEECH AND SCENE ANALYSIS, COMPUTER VISION AND GRAPHICS, AND SO FORTH. TO SERVE THIS NEED, A NEW AND POWERFUL CLASS OF DIGITAL PROCESSOR AND ARCHITECTURE IS PROPOSED. THE NEW DIGITAL PROCESSOR REPRESENTS A POSSIBLE BREAKTHROUGH IN THE AREAS OF SPEED, AREA-SPEED AND COST-PERFORMANCE MEASURES. IT IS UNIQUE IN THAT IT CAN PROVIDE MULTI-MEGAHERTZ FIXED AND FLOATING POINT OPERATION ON ONE VLSI CHIP. ITS INNOVATIVE BIT-SERIALINTERPROCESSOR I/O STRUCTURE MAKES IT AN IDEAL CANDIDATE FORFINE-GRAIN SYSTOLIC ARRAY APPLICATIONS. THE FINAL RESULT SHOULD BE A SYSTEM WHICH ACHIEVES THE TARGET 10(7-8) MFLOP PER CHIP COMPUTATIONAL BANDWIDTH IN A SMALL, LOW COST PACKAGE. FOR THE FIRST TIME, ESSENTIALLY A DESKTOP SUPERCOMPUTER WOULD BE AVAILABLE. SUCH A MACHINE WOULD HAVEIMMEDIATE ACCEPTANCE AS AN ATTACHED CO-PROCESSOR IN GENERAL APPLICATION OR EMBEDDED INTO SIGNAL AND IMAGING SYSTEMS IN APPLICATION SPECIFIC ENVIRONMENTS.

* Information listed above is at the time of submission. *

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