VECTOR PROCESSORS FOR SYSTOLIC ARRAYS

Award Information
Agency:
National Science Foundation
Branch
n/a
Amount:
$50,000.00
Award Year:
1989
Program:
SBIR
Phase:
Phase I
Contract:
n/a
Agency Tracking Number:
10693
Solicitation Year:
n/a
Solicitation Topic Code:
n/a
Solicitation Number:
n/a
Small Business Information
Peregrine Engineering
3424 Nw 31st St, Gainesville, FL, 32605
Hubzone Owned:
N
Socially and Economically Disadvantaged:
N
Woman Owned:
N
Duns:
n/a
Principal Investigator:
Michael F Griffin
Principal Investigator
(904) 371-2567
Business Contact:
() -
Research Institution:
n/a
Abstract
THE DIGITAL SIGNAL AND IMAGE PROCESSING INDUSTRY CONTINUES TO ENJOY PHENOMENAL GROWTH. HOWEVER, MANY COMPUTER-BOUND, HIGH-END, REAL-TIME NEEDS ARE NOT CURRENTLY BEING MET. APPLICATION AREAS TYPIFYING THESE REQUIREMENTS ARE COMMUNICATIONS, RADAR/SONAR, SPEECH AND SCENE ANALYSIS, COMPUTER VISION AND GRAPHICS, AND SO FORTH. TO SERVE THIS NEED, A NEW AND POWERFUL CLASS OF DIGITAL PROCESSOR AND ARCHITECTURE IS PROPOSED. THE NEW DIGITAL PROCESSOR REPRESENTS A POSSIBLE BREAKTHROUGH IN THE AREAS OF SPEED, AREA-SPEED AND COST-PERFORMANCE MEASURES. IT IS UNIQUE IN THAT IT CAN PROVIDE MULTI-MEGAHERTZ FIXED AND FLOATING POINT OPERATION ON ONE VLSI CHIP. ITS INNOVATIVE BIT-SERIALINTERPROCESSOR I/O STRUCTURE MAKES IT AN IDEAL CANDIDATE FORFINE-GRAIN SYSTOLIC ARRAY APPLICATIONS. THE FINAL RESULT SHOULD BE A SYSTEM WHICH ACHIEVES THE TARGET 10(7-8) MFLOP PER CHIP COMPUTATIONAL BANDWIDTH IN A SMALL, LOW COST PACKAGE. FOR THE FIRST TIME, ESSENTIALLY A DESKTOP SUPERCOMPUTER WOULD BE AVAILABLE. SUCH A MACHINE WOULD HAVEIMMEDIATE ACCEPTANCE AS AN ATTACHED CO-PROCESSOR IN GENERAL APPLICATION OR EMBEDDED INTO SIGNAL AND IMAGING SYSTEMS IN APPLICATION SPECIFIC ENVIRONMENTS.

* information listed above is at the time of submission.

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