High Speed Analog to Digital Converter Technology

Current advanced as well as future electronic data communications and signal processing requirements for military as well as commercial applications need the operations of analog to digital converters (ADCs) with performances beyond that of commercially available designs. In this Phase I proposal, PRI will develop the architectural design for a new integrated circuit chip set to be housed in a single multi-chip module. This ADC concept consists of an array of bandpass sigma-delta modulator-based ADCs combined with a digital self-calibration scheme. Simulations and analysis will be performed on a 16-bit, 200Ms/s design to establish the feasibility of such a scheme. The bandpass sigma-delta ADC will be based on a PRI design developed on a previous DARPA-sponsored SBIR. Higher resolution will be achieved by using a 3-bit quantizer instead of the 1-bit used in our previous design. The bandpass sigma-delta modulator concept achieves high resolution by over-sampling and noise shaping as demonstrated in our previous work. Decimation filters at the output will filter the shaped quantization noise and provide the desired ADC output. High bandwidths can be achieved by an array of these ADCs where the signals of each ADC are combined to form the final output.