Design of GPS Receiver Module on a Single Silicon Chip

Award Information
Agency: Department of Defense
Branch: Defense Advanced Research Projects Agency
Contract: N/A
Agency Tracking Number: 35716
Amount: $376,363.00
Phase: Phase II
Program: SBIR
Awards Year: 1998
Solicitation Year: N/A
Solicitation Topic Code: N/A
Solicitation Number: N/A
Small Business Information
25500 Hawthorne Blvd., Suite, 2300, Torrance, CA, 90505
HUBZone Owned: N
Woman Owned: N
Socially and Economically Disadvantaged: N
Principal Investigator
 Reza Rofougaran
 (310) 378-0056
Business Contact
Phone: () -
Research Institution
Recent years have seen the size of GPS receivers shrink dramatically due to higher levels of integration. A GPS receiver consists of a combination of RF and IF circuitry, filters, analog to digital converts (ADC) and a digital Signal Processor (DSP) engine. One of the remaining factors preventing further integration is the necessity of a Surface Acoustic Wave (SAW) filter and dielectric filters. These filters are usually large in size compared to the chip package and can be expensive. We are proposing a solution to these problems by integrating all external functions and components such as filters, the Oscillator tank circuitry, and the DSP engine onto a single substrate, reducing the size and cost. Because this chip would be CMOS, adding a digital demodulator will be trivial. In addition, we will add programmability to the GPS receiver that will allow it to demodulate all aspects of the GPS signals in both RF bands. We can achieve these goals through an innovative architecture and state-of-the-art circuit design. This level of integration has not yet been achieved because the necessary circuits and techniques have only been pioneered and demonstrated in the past few years by our design team.

* Information listed above is at the time of submission. *

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