Low Cost 10 Gb/s Optical Links for Gigabit Networks
Department of Energy
Agency Tracking Number:
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Small Business Information
Princeton Electronic Systems,i
PO Box 8627, Princeton, NJ, 08543
Socially and Economically Disadvantaged:
AbstractNot Available Special technology and circuit architecture is under investigation for implementation of radiation hard low power electronics (LPE) which operate at low supply voltages and consume low power levels without sacrificing performance. Silicon-on-Insulator (SOI) substrates have advantages which make it attractive for applications that require tolerance to radiation effects. A significant aspect regarding commercial application of SOI is the inconsistency of the gate oxide integrity (GOI) of CMOS circuitry. The variation in the gate oxide breakdown may be attributed to such material factors as surface roughness, defect density or metallics. Testing is typically expensive and time consuming. An opportunity exists to establish a test methodology for starting SOI material using pseudo gate oxide structures and a polysilicon or metallic dot method of ramped voltage stress testing. In addition, a detailed examination of pseudo gate oxide integrity will be examined as a function of SOI surface roughness. A matrix of as-received and smoothed SOI surfaces will be examined using a 3-point pseudo gate oxide test method that requires a simple oxidation and dot contact process. Surface smoothing will be implemented using a novel gas cluster ion beam technology (GCIB). Commercialization of both the GOI test methodology and the GCIB smoothing is regarded with high probability.
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