ADVANCED GENERAL PURPOSE CONTROLLER

Award Information
Agency: Department of Defense
Branch: Navy
Contract: N/A
Agency Tracking Number: 6298
Amount: $531,000.00
Phase: Phase II
Program: SBIR
Awards Year: 1988
Solicitation Year: N/A
Solicitation Topic Code: N/A
Solicitation Number: N/A
Small Business Information
504 Monterey Dr, Aptos, CA, 95004
DUNS: N/A
HUBZone Owned: N
Woman Owned: N
Socially and Economically Disadvantaged: N
Principal Investigator
 Robert Murphy
 (408) 662-0432
Business Contact
Phone: () -
Research Institution
N/A
Abstract
CURRENT CONTROLLER METHODOLOGY IS BASED ON THE PREMISE THAT REAL-TIME APPLICATIONS WILL EXECUTE WITHIN A WELL UNDERSTOOD ENVIRONMENT WITH CLEARLY DEFINED LIMITS. THESE CONTROLLERS DO NOT ADDRESS PROBLEMS OF APPLICATION DEVELOPMENT AND MAINTENANCE FOR TARGET ENVIRONMENTS WHOSE LIMITS MAY NOT BE KNOWN, WHERE HOST SYSTEMS ARE CUMBERSOME, WHERE PERFORMANCE REQUIREMENTS CHANGE, OR WHERE EMULATORS ARE INADEQUATE. QSD, WHOSE PRINCIPALS DEVELOPED THE FIRST FORTH LANGUAGE DIRECT EXECUTION MICROPROCESSOR, THE NOVIX NC4000, PROPOSE TO PROVIDE A CONTROLLER THAT SOLVES THESE PROBLEMS USING THE FOLLOWING TECHNIQUES: 1. MULTIPLE STACK RISC ARCHITECTURE - YIELDS MINIMUM HARDWARE WITH COMPACT MACHINE CODE. 2. INSITU DEVELOPMENT - TARGET-RESIDENT COMPILER/TOOLS PERMIT CONTROLLER APPLICATIONS TO BE DEVELOPED WITHOUT TRADITIONAL IN-CIRCUIT-EMULATORS. 3. HIGH SPEED INTER-PROCESSOR COMMUNICATIONS - THROUGH STACK SHARING TECHNIQUES, DATA RATES OF 16 MEGABYTES PER SECOND CAN BE ACHIEVED IN THE FORMATION OF NETWORKS. 4. CO-PROCESSOR SUPPORT - HIGH SPEED COMMUNICATION WITH MATH OR DSP CO-PROCESSOR IS SUPPORTED THROUGH A DEDICATED PARALLEL BUS. 5. FORTHAS INTERMEDIATE CODE - REVERSE POLISH NOTATION STREAMLINES INTERMEDIATE CODE TO SUPPORT THE DEVELOPMENT OF HIGH LEVEL LANGUAGE COMPILERS/TOOLS, WHILE THE DIRECT EXECUTION OF INTERMEDIATE CODE ACCELERATES PERFORMANCE OF PROGRAMS WRITTEN IN HIGH LEVEL C, ADA, PASCAL, ETC.

* Information listed above is at the time of submission. *

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