GALLIUM ARSENIDE MEMORY APPLICATION STUDY Q-DOT RESEARCH

Award Information
Agency:
Department of Defense
Branch
Air Force
Amount:
$500,000.00
Award Year:
1985
Program:
SBIR
Phase:
Phase II
Contract:
n/a
Award Id:
1030
Agency Tracking Number:
1030
Solicitation Year:
n/a
Solicitation Topic Code:
n/a
Solicitation Number:
n/a
Small Business Information
1069 Elkton Drive, Colorado Springs, CO, 80907
Hubzone Owned:
N
Minority Owned:
N
Woman Owned:
N
Duns:
n/a
Principal Investigator:
Dr. Peter C. T. Roberts
(303) 590-1112
Business Contact:
() -
Research Institution:
n/a
Abstract
TO SUCCESSFULLY EMPLOY THE INTRINSICALLY SHORT ACCESS TIME (I.E., LESS THAN 1NS) OF GAAS DIGITAL MEMORY CHIPS, UNIQUE SIGNAL PROCESSING ARCHITECTURES WILL BE REQUIRED WHICH MAY INFLUENCE CONVENTIONAL FUNCTION PARTITIONING AMONG INTEGRATED CIRCUITS. TO DETERMINE THE OPTIMAL ARCHITECTURE OF BOTH PROCESSOR AND IC'S, A CANDIDATE PROCESSOR OF IMPORTANCE TO THE AIR FORCE WILLL BE SELECTED. ITS ARCHITECTURE WILL BE ANALYZED TO UNCOVER OPPORTUNITIES FOR IMPROVEMENT. THE ARCHITECTURE WILL BE OPTIMIZED FOR GAAS MEMORY. RESULTING STRUCTURES WILLL BE SIMULATED AT BOTH THE CIRCUIT AND SYSTEM LEVELS. BENEFITS OF INTEGRATED LOGIC-MEMORY WILL BE COMPARED TO CONVENTIONAL IMPLEMENTATIONS. A COMPREHENSIVE FINAL REPORT WILL DOCUMENT THE RESULTS.

* information listed above is at the time of submission.

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