ASSESSMENT OF 10(14) GATE-HZ/CM(2) CHARGE-MODE LOGIC FOR SUPERCOMPUTERS

Award Information
Agency: Department of Energy
Branch: N/A
Contract: N/A
Agency Tracking Number: 1156
Amount: $488,533.00
Phase: Phase II
Program: SBIR
Awards Year: 1985
Solicitation Year: N/A
Solicitation Topic Code: N/A
Solicitation Number: N/A
Small Business Information
1069 Elkton Dive, Colorado Springs, CO, 80907
DUNS: N/A
HUBZone Owned: N
Woman Owned: N
Socially and Economically Disadvantaged: N
Principal Investigator
 Peter C.t. Roberts
 Director Adv. S.s. Tech
 () -
Business Contact
Phone: () -
Research Institution
N/A
Abstract
CHARGE-MODE DIGITAL LOGIC APPEARS TO HAVE GREAT POTENTIAL AS A BUILDING BLOCK FOR FUTURE SUPERCOMPUTERS. ITS EXTREMELY HIGH COMPUTATIONAL DENSITY, ESTIMATED AT 2 X 10(14) GATE-HZ/CM(2), IS ACHIEVABLE AT 2 MINIMUM FEATURES USING CONVENTIONAL, OPTICAL LITHOGRAPHY. BY CONTRAST, DOD'S VHSIC II PROGRAM GOAL IS 1 X 10(13) GATE-HZ/CM(2) AND REQUIRES 0.5 UPSILON M FEATURES. WITH CHARGE-MODE LOGIC, MORE THAN 20,000 8-BIT TIMES 8-BIT, 2'S COMPLEMENT MULTIPLIERS CAN BE FABRICATED ON A 1.0 CM(2) CHIP YIELDING 17 X 10(9) MULTIPLICATIONS PER SECOND. IN ORDER TO EFFECTIVELY UTILIZE SUCH A LARGE COMPUTATIONAL SWNMAIRY, PEOXWAAOEA MUAR VW EENFWS IN XEWDULLY OESWEWS ARRAY (E.G., A SYSTOLIC ARRAY). PRELIMINARY DESIGNS OF CHARGE-MODE LOGIC COMPONENTS LEND THEMSELVES WELL TO ORDERED ARRAYS, ESPECIALLY THOSE SUITABLE FOR MATRIX-MATRIX AND MATRIX-VECTOR OPERATIONS. THROUGH DETAILED MODELING AND ANALYSIS, THE PHASE I EFFORT WILL RESULT IN CANDIDATE COMPONENTS TO BE FABRICATED IN PHASE II.

* Information listed above is at the time of submission. *

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