Low-Phase-Noise, Phase-Locked Miniature Oscillator (PL MINO) for Advanced ADCs(9664)
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1069 Elkton Drive, Colorado Springs, CO, 80907
AbstractQ-DOT proposes to develop a low-noise, phase-locked, miniature oscillator (PL MINO) for use in advanced communications systems. The PL MINO will provide the low-noise, 2.5 GHz clock waveform for next generation ADCs in a 0.33 cm3 (0.02 in3) package. It will be a dramatic advancement over state-of-the-art, rack-mounted clock oscillators available today. The PL MINO circuitry will be realized in IBM's SiGe BiCMOS technology. The phase-locked loop (PLL) will be closed around the free-funning MINO (FR MINO) that is in ongoing development at Q-DOT. The FR MINO uses a surface transversal wave (STW) resonator built by RF Monolithics to provide very low phase noise in a very small package. The first generation FR MINO achieved a jitter of 19 fs. A refinement of the FR MINO currently in progress is expected to reduce the jitter to 7 fs. The PLL circuitry will be designed, fabricated, packaged, and tested under the proposed Phase II program. The SiGe chip, STW resonator, and/or package will be refined as necessary during the Phase II+ to optimize performance prior to production. Under the proposed Phase II Option, a FR MINO will be built using an over-moded sapphire resonator from TFR Technologies to further reduce the close-in phase noise by up to 20 dB for use as a local oscillator in next-generation radars.
* information listed above is at the time of submission.