SI/GE OPTICAL BUS ARRAY AND BINARY FANOUT HOLOGRAM FOR SI-BASED VLSI WAFER-SCALE OPTOELECTRONIC INTERCONNECTS

Award Information
Agency:
Department of Defense
Amount:
$59,996.00
Program:
SBIR
Contract:
N/A
Solitcitation Year:
N/A
Solicitation Number:
N/A
Branch:
Missile Defense Agency
Award Year:
1994
Phase:
Phase I
Agency Tracking Number:
25594
Solicitation Topic Code:
N/A
Small Business Information
Radiant Research Laboratory
10306 Sausalito Drive, Austin, TX, 78759
Hubzone Owned:
N
Woman Owned:
N
Socially and Economically Disadvantaged:
N
Duns:
N/A
Principal Investigator
 Suning Tang, Phd
 (512) 343-1951
Business Contact
Phone: () -
Research Institution
N/A
Abstract
We propose a dratically new optoelectronic chip modules (OCMs) concepts to optically interconnect Si-based VLSI wafer-scale integrated circuits. Realizing the fact that system clock speed is three to five times higher than that ofprocessor speed, we propose to develop an optical clock signal distribution networks for wafer-scale interconnects. The architecture is to employ a superstrate Si/Ge waveguide array as the optical bus for signal distribution. Implementation of a waveguide layer on top of the Si-based VLS/ULSI circuit is due to the fact that the real estate of the Si wafer is already occupied by high packaging density transistors and logic gates. Broadcasting of clock signal requires another physical layer through which optical signal can be fanned out as requested.

* information listed above is at the time of submission.

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