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Brassboard Implementation of a Wideband Digital Beamforming and Direction Finding Receiver

Award Information
Agency: Department of Defense
Branch: Navy
Contract: N00178-05-C-3058
Agency Tracking Number: N032-0731
Amount: $966,002.00
Phase: Phase II
Program: SBIR
Solicitation Topic Code: N03-215
Solicitation Number: 2003.2
Timeline
Solicitation Year: 2003
Award Year: 2005
Award Start Date (Proposal Award Date): 2005-08-18
Award End Date (Contract End Date): 2008-08-31
Small Business Information
329 North Bernardo Avenue
Mountain View, CA 94043
United States
DUNS: 626626782
HUBZone Owned: No
Woman Owned: No
Socially and Economically Disadvantaged: No
Principal Investigator
 STEPHEN BRUZZONE
 Director, Advanced Techno
 (650) 988-4723
 bruzzone@radixtek.com
Business Contact
 Dennis Kanemura
Title: VP, Operations and COO
Phone: (650) 988-4702
Email: dkanemur@radixtek.com
Research Institution
N/A
Abstract

The increasing interference density of the modern RF environment is causing unacceptable degradation to the effectiveness of military electronic support (ES) and radar warning systems, which for economy must use wideband analog detection and discrimination devices in their front-end processing stages. A Phase I SBIR study was completed in 2004, which showed that the core technology could be upgraded to operate through relatively severe interference environments, by replacing the DSP algorithms applied to the standard digitized outputs from these analog front-ends. DSP retrofits were demonstrated on the Phase I study both for instantaneous frequency measurement (IFM) systems and wideband direction-finding (WDF) systems. Through computer modeling and simulation, the proposed DSP algorithms were shown to maintain effective operation through up to 40 dB of interference, and to be highly robust to non-ideal hardware characteristics. The Phase II program proposed herein will construct a brassboard implementation to retire the remaining technical risk, by replacing computer models with actual analog hardware. It is divided into three sub-phases as follows: A Base Effort, to implement and prove the basic technique in brassboard form, through controlled laboratory tests using digitized snapshots from actual analog hardware; An Option 1 Effort, to implement and demonstrate the objective IFM and WDF processors in similar brassboard form; And an Option 2 effort, to define the real-time retrofit product architecture.

* Information listed above is at the time of submission. *

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