Characterization and Mitigation of Radiation Effects in Nonplanar Nano-technology Microelectronics

Award Information
Agency:
Department of Defense
Branch:
Defense Threat Reduction Agency
Amount:
$99,964.00
Award Year:
2010
Program:
SBIR
Phase:
Phase I
Contract:
HDTRA1-10-P-0024
Agency Tracking Number:
T092-001-0056
Solicitation Year:
2009
Solicitation Topic Code:
DTRA092-001
Solicitation Number:
2009.2
Small Business Information
CFD Research Corporation
215 Wynn Dr., 5th Floor, Huntsville, AL, 35805
Hubzone Owned:
N
Socially and Economically Disadvantaged:
N
Woman Owned:
Y
Duns:
185169620
Principal Investigator
 Marek Turowski
 Director of Nano Electronics
 (256) 726-4800
 tsb@cfdrc.com
Business Contact
 Deb Phipps
Title: Senior Contract Specialist
Phone: (256) 726-4884
Email: dap@cfdrc.com
Research Institution
N/A
Abstract
Future high-performance integrated circuits in DoD satellite systems will require non-planar nano-technology devices, such as MultiGate Field Effect Transistors (MuGFET) or FinFET, which can decrease pattern area of logic circuits below 50% of the conventional planar technologies. The International Technology Roadmap for Semiconductors predicts that such devices will be the cornerstone of sub-32nm technologies. However, the single-event-effect (SEE) response of non-planar devices and circuits is unknown. To enable characterization and mitigation of SEEs in such technologies, CFDRC, in collaboration with Vanderbilt University (VU), Texas Instruments (TI), and SEMATECH, proposes the following innovations: (a) First ever characterization, by modeling and experiments, of SEEs in non-planar nano-scale FinFET devices and circuits; (b) New semiconductor physics models for the nano-technologies: microscopic charge generation and deposition, electron/hole transport in insulators (new high-k dielectrics) and insulator-silicon interfaces, implemented in CFDRC’s NanoTCAD 3D/mixed-mode simulator; (c) Simulation-supported design and validation of mitigation techniques for SEEs. In Phase I, representative advanced FinFET devices and circuits will be used for ‘proof-of-concept’ modeling, validated with TI data, and characterized for SEEs by means of 3D/mixed-mode simulations. Plans for SEE mitigation methods will be developed. In Phase II, NanoTCAD will be enhanced with the new models and SEE mitigation methods will be explored, verified, and demonstrated.

* information listed above is at the time of submission.

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