Processing Signals In High Density Electromagnetic Environments

Award Information
Agency:
Department of Defense
Branch
Navy
Amount:
$99,991.00
Award Year:
2008
Program:
SBIR
Phase:
Phase I
Contract:
N65538-08-M-0131
Agency Tracking Number:
N082-165-0004
Solicitation Year:
2008
Solicitation Topic Code:
N08-165
Solicitation Number:
2008.2
Small Business Information
RESEARCH ASSOC. OF SYRACUSE
6780 Northern Blvd, Ste 100, East Syracuse, NY, 13057
Hubzone Owned:
N
Socially and Economically Disadvantaged:
N
Woman Owned:
N
Duns:
153924188
Principal Investigator:
Skip Mansur
Principal Investigator
(315) 339-4800
smansur@ras.com
Business Contact:
Stan Hall
VP of Operations
(315) 463-2266
shall@ras.com
Research Institution:
n/a
Abstract
Signal detection and measurement of signals of interest in the presence of high power in-band emissions from own-ship emitters using a multi-pronged system approach is proposed versus using one single technique. Due to the large signal levels of on-board emitters and resulting large dynamic range under which low-level signals must be detected while maintaining spectral coverage, RAS proposes a suite of techniques starting with the Electronic Support system front-end to mitigate RF component saturation through the customized signal detection and processing paths. Adaptive signal suppression is incorporated with RF selectable filtering, attenuation, and/or limiting. Signal processing techniques include time-frequency excision of large signals, pulse interference detection and characterization and ICA. Existing RAS FPGA designs and expertise for real-time parameter measurements, advanced techniques for characterizing intentional modulation on pulse, precision parameter measurement, Fourier transforms, and Wigner-Ville / Hough processing will be leveraged. Automatic resource management and knowledge and use of own-ship radar transmission parameters and timing will be included based on SEWIP Block 2 architectures. Requirements and the system architecture will be developed and algorithms characterized using a MATLABTM model. The hardware feasibility study will establish a baseline for Phase II development in open architecture COTS hardware.

* information listed above is at the time of submission.

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