Cognitive Processing Hardware/Software Elements
Small Business Information
632 Broadway, Suite 803, New York, NY, 10012
AbstractRecently, solvers for the Satisfiability problem (SAT) have proved to be an enabling technology for diverse application areas including planning, cryptography, hardware verification, and software verification. However, solver performance, in terms of speed, maximum problem size, and efficiency, is a limiting factor to the more extensive application of the technology. We have developed novel problem representations, algorithms, and heuristics that improve the performance of SAT solvers over existing approaches. Our analysis shows that these developments will provide a performance improvement of 2 to 3 orders of magnitude in terms of solver speed and maximum problem size. We propose to realize these improvements by developing a prototype parallel SAT solver and a compiler. This implementation will be the basis of a product, code named AlefT, which we will license to the planning and verification market segments.
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