Optimizing and Mapping Tool Chain for FPGA Programming
Small Business Information
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AbstractIn this Phase I SBIR project, we will produce a plan and feasibility study for improvements in tools through the use and improvement advanced high-level program optimization and mapping technologies, coupled with low-level tools that render programs to FPGAs, within the context of an embedded middleware working group. This work will be performed within the context of the Morphware Forum stnards. Our designs will be motivated by a requirements-gathering, metrics design, and competitive analysis based on commercial product design methodologies.
* information listed above is at the time of submission.