Optimizing and Mapping Tool Chain for FPGA Programming

Award Information
Agency: Department of Defense
Branch: Defense Advanced Research Projects Agency
Contract: W31P4Q-08-C-0319
Agency Tracking Number: 06SB2-0112
Amount: $749,928.00
Phase: Phase II
Program: SBIR
Awards Year: 2008
Solicitation Year: 2006
Solicitation Topic Code: SB062-006
Solicitation Number: 2006.2
Small Business Information
632 Broadway, Suite 803, New York, NY, 10012
DUNS: 022423854
HUBZone Owned: N
Woman Owned: N
Socially and Economically Disadvantaged: N
Principal Investigator
 Richard Lethin
 Directing Engineer
 (212) 780-0527
 lethin@reservoir.com
Business Contact
 Melanie Peters
Title: Business Manager
Phone: (212) 780-0527
Email: peters@reservoir.com
Research Institution
N/A
Abstract
Field Programmable Gate Arrays (FPGAs) are an important technology for many DoD and commercial high performance computing applications. A number of supercomputing, workstation, and embedded computing hardware platforms have emerged recently to supply FPGA computing power for these applications. Unfortunately, developing for these platforms is currently a long, difficult and error-prone process. While a number of commercial software tools are emerging to facilitate programming beyond VHDL, the high-level application mapping problem to heterogeneous complexes of general purpose processors and FPGAs is still a complex manual programming task. In this Phase II SBIR project, we will modify the R-Stream® high-level compiler to automatically map programs expressed in C to such heterogeneous complexes. This technology will be applicable to a range of system targets including supercomputers, workstations, and high performance embedded computing systems. R-Stream will emit mapped programs in a “lower-level” language that is used to express computations to be performed on individual FPGAs, as well as the choreography of computation among these devices. Our Phase I project established the feasibility of extending R-Stream for this purpose. The benefit of this project is that it will improve productivity, portability of programming systems employing FPGAs, as well as improved quality of the mappings that are achieved.

* Information listed above is at the time of submission. *

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