Effect of Analog Built-in Self Test (BIST) on a Flash Analog-to-Digital Converter's (ADC) Radiation Effects Behavior

Award Information
Agency: Department of Defense
Branch: Navy
Contract: N00178-04-C-3015
Agency Tracking Number: N022-1185
Amount: $599,815.00
Phase: Phase II
Program: SBIR
Awards Year: 2004
Solicitation Year: 2002
Solicitation Topic Code: N02-205
Solicitation Number: 2002.2
Small Business Information
7070 North Oracle Road Suite 120, Tucson, AZ, 85704
DUNS: 157955597
HUBZone Owned: N
Woman Owned: Y
Socially and Economically Disadvantaged: N
Principal Investigator
 Bert Vermeire
 Chief Technical Officer
 (520) 742-3300
Business Contact
 Douglas Goodman
Title: CEO
Phone: (520) 742-3300
Email: doug@ridgetop-group.com
Research Institution
The continuous increase in integrated circuit (IC) scaling and complexity means that there are less output pins per transistor on the chip, resulting in reduced observability, controllability and insufficient test coverage. External testing of the IC has therefore become complex, time intensive and expensive. The answer is to use Built In Self Test (BIST). The use of BIST can, however, affect the way in which a circuit responds to a radiation event because it is intimately electrically connected to the circuit it is to test. The technical objective of the Phase I project was to develop an innovative feasibility concept that provides a radiation hard by design capability for BIST circuitry in a chosen manufacturing technology, and incorporate this concept into a selected commercial electronic design automation (EDA) tool. The test circuit selected for the radiation effects study and subsequent hardening is a flash Analog-to-Digital Converter (ADC) with non-linearity BIST and prognostic BIST. During Phase I the design of this circuit was completed and radiation effects vulnerability studies were performed. Some hardening strategies have been incorporated. Concepts for tools that would allow design automation of some of the tasks necessary to achieve a radiation-hardened design have also been developed in parallel. The ADC and the BIST circuits were entered into an EDA design system having circuit simulation capabilities (using the Cadence EDA framework). With the successful simulation results from Phase I, the technical objective of Phase II is to move forward and conduct a prototype demonstration. Final deliverables will include a qualified library of BIST for mixed signal designs, a high-speed hardened flash ADC core and a new and unique design kit for radiation effects modeling of analog and mixed signal circuits.

* Information listed above is at the time of submission. *

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