Highly Integrated Silicon (Si)-based RF electronics

Award Information
Agency: Department of Defense
Branch: Defense Advanced Research Projects Agency
Contract: W31P4Q-09-C-0243
Agency Tracking Number: 08SB2-0724
Amount: $98,999.00
Phase: Phase I
Program: SBIR
Awards Year: 2009
Solicitation Year: 2008
Solicitation Topic Code: SB082-044
Solicitation Number: 2008.2
Small Business Information
RNET Technologies, Inc.
240 W. Elmwood Dr., Suite 2010, Dayton, OH, 45459
DUNS: 141943030
HUBZone Owned: N
Woman Owned: N
Socially and Economically Disadvantaged: N
Principal Investigator
 Todd Grimes
 Project Manager
 (937) 433-2886
 tgrimes@Rnet-Tech.com
Business Contact
 V. Nagarajan
Title: President
Phone: (937) 433-2886
Email: vnagarajan@Rnet-Tech.com
Research Institution
N/A
Abstract
The solicitation indicates that the objective is to develop methods to achieve unparalleled levels of integration for silicon-based RF electronics in support of emerging DoD-critical applications. Example DoD applications include wafer-scale phase array radars, highly integrated warfare systems, or compact sensing systems. In the commercial sector, applications may include wireless voice/data communications, industrial control and automation, automotive radar, etc. Recent advancements in silicon-based technologies have allowed transistor performance to approach cutoff frequencies normally reserved for III-V semiconductor materials, thus making them suitable for integration into various DoD-critical RF applications. We are planning to utilize the latest multi-gate MOSFET technology to develop RF building blocks to achieve highly integrated, low-power RF designs. Multi-gate MOSFETs differ from typical transistor implementations, as they contain additional gates that maybe utilized to “tune” circuit performance and characteristics while reducing the overall size of the design. These devices also offer excellent mixed-signal alternatives, as they possess architectural features conductive to the integration of analog and digital building blocks on the same substrate with minimal overhead to the fabrication sequence; reduced cross-talk and better isolation on SOI platform, multi-finger gates, minimal parasitics, scalability and simplicity.

* information listed above is at the time of submission.

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