Innovative Approaches to Low Power, Sub-Threshold Electronic Circuits

Award Information
Agency: Department of Defense
Branch: Defense Advanced Research Projects Agency
Contract: W31P4Q-09-C-0393
Agency Tracking Number: 08SB2-0732
Amount: $98,999.00
Phase: Phase I
Program: SBIR
Awards Year: 2009
Solicitation Year: 2008
Solicitation Topic Code: SB082-045
Solicitation Number: 2008.2
Small Business Information
240 W. Elmwood Dr., Suite 2010, Dayton, OH, 45459
DUNS: 141943030
HUBZone Owned: N
Woman Owned: N
Socially and Economically Disadvantaged: N
Principal Investigator
 Todd Grimes
 Project Manager
 (937) 433-2886
Business Contact
 V. Nagarajan
Title: President
Phone: (937) 433-2886
Research Institution
Recently, the DoD has become interested in technologies that can maximize processing energy efficiency and power savings, while maintaining reasonable performance. It particular, sub-threshold digital circuit operation is of the up-most interest for ultra-low power (ULP) military processing systems. In Phase I, a generic ULP field programmable gate array (FPGA) architecture capable of both sub-threshold and super-threshold operation will be developed. In sub-threshold mode, VDD is set less than VT, resulting in circuit which operates at a lower frequency with dramatic power savings. Super-threshold mode refers to the normal operating mode which provides higher performance during burst modes. As an innovative approach to meet the requirements of this solicitation, we are planning to design, simulate, fabricate, and characterize a general ULP FPGA device by the end of Phase II. This device will have the ability to dynamically switch between sub-threshold and super-threshold modes of operation depending the required device functionality, performance, and power. This technology will provide “added value” for various military and commercial applications.

* Information listed above is at the time of submission. *

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