THE BULK-STORAGE MODULE FOR FASTBUS MEMORY APPLICATIONS

Award Information
Agency: Department of Energy
Branch: N/A
Contract: N/A
Agency Tracking Number: 7070
Amount: $500,000.00
Phase: Phase II
Program: SBIR
Awards Year: 1988
Solicitation Year: N/A
Solicitation Topic Code: N/A
Solicitation Number: N/A
Small Business Information
Scientific Systems Intl
3491 B Trinity Dr, Los Alamos, NM, 87544
DUNS: N/A
HUBZone Owned: N
Woman Owned: N
Socially and Economically Disadvantaged: N
Principal Investigator
 Mr Donald R Machen
 (505) 662-6712
Business Contact
Phone: () -
Research Institution
N/A
Abstract
THE FASTBUS SYSTEM SPECIFICATION FOR HIGH-ENERGY PHYSICS AND OTHER DATA SYSTEM APPLICATIONS DEFINES A LARGE ADDRESS SPACE IN WHICH SUPPORT MODULES MAY RESIDE ON CONNECTED SEGMENTS. THE INCREASING NUMBER OF EXPERIMENTS IN THE PHYSICAL SCIENCES USING FASTBUS DICTATES THAT THE SPECTRUM OF SUPPORT MODULES MUST CONTINUE TO GROW AND BE EXTENDED CAPABILITY. AT PRESENT, THE VARIETY OF FASTBUS MEMORY MODULES AND THE SCOPE OF THEIR FUNCTIONS ARE LIMITED. FEATURES OF THE FASTBUS PROTOCOL HAVE NOT BEEN EFFECTIVELY USED TO HELP INCREASE THE AVAILABLE DATA STORAGE SPACE AND PERFORMANCE FOR LARGE MEMORY CONFIGURATIONS. A BULK-STORAGEMODULE (BSM) WILL BE DEVELOPED HAVING COMPREHENSIVE FUNCTIONS TO SERVE AS A STANDARD MEMORY ELEMENT FOR FASTBUS APPLICATIONS. THE BSM WILL CONTAIN AT LEAST 8 MEGAWORDS OF HIGH-SPEED STORAGE THAT CAN EASILY BE UPGRADED AS THE SEMICONDUCTOR INDUSTRY INCREASES THE DENSITY OF ITS MEMORY-INTEGRATED CIRCUITS. ADDITIONALLY, THE BSM WILL FEATURE MEMORY-INTERLEAVING AND HISTOGRAMMING CAPABILITIES THAT USE THE FASTBUS PROTOCOL TO ACHIEVE A MANY-FOLD INCREASE IN BOTH SPEED AND STORAGE CAPACITY WITHIN A FASTBUS SYSTEM. AN INTERLEAVED BSM MEMORY SYSTEM COULD EASILY REACH A CAPACITY OF 512 MEGABYTES PER CRATE, COMPARABLE TO THE SIZE OF DISK DRIVES INSTALLED ON MANY HOST COMPUTER SYSTEMS. THE FEASIBILITY DETERMINATION THAT WILL BE MADE DURING THE PHASE I RESEARCH WILL INCLUDE A SYSTEM DESIGN OF THE BSM; SELECTION OF THE INITIAL MEMORY ELEMENT TO PROVIDE AT LEAST AN 8-MEGAWORD, 32-BIT ERROR-CORRECTED MEMORY IN A CONFIGURATION THAT WILL ALLOW THE MODULE TO BE UPGRADED EASILY; AND DEVELOPMENT OF INTERLEAVING AND AUTOMATIC HISTOGRAMMING TECHNIQUES FOR A BSM THAT USES THE FASTBUS PROTOCOL TO GAIN SPEED AND OVERALL CAPACITY.

* information listed above is at the time of submission.

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