Hybrid CMOS/Nanodevice Integrated Circuits

Award Information
Agency: Department of Defense
Branch: Air Force
Contract: FA9550-07-C-0080
Agency Tracking Number: F074-025-0371
Amount: $99,789.00
Phase: Phase I
Program: STTR
Awards Year: 2007
Solicitation Year: 2007
Solicitation Topic Code: AF07-T025
Solicitation Number: N/A
Small Business Information
SENSOR ELECTRONIC TECHNOLOGY, INC.
1195 Atlas Road, Columbia, SC, 29209
DUNS: 135907686
HUBZone Owned: N
Woman Owned: N
Socially and Economically Disadvantaged: N
Principal Investigator
 Nezih Pala
 Research Scientist
 (803) 647-9757
 pala@s-et.com
Business Contact
 Remis Gaska
Title: President and CEO
Phone: (803) 647-9757
Email: gaska@s-et.com
Research Institution
 STONY BROOK UNIV.
 Lydia Chabza
 Research Foundation
Office of Sponsor Programs
Stony Brook, NY, 11794-3362
 (631) 632-4402
 Nonprofit college or university
Abstract
Ultra-dense integrated circuits with sub-10-nm features would provide enormous benefits for all information technologies, including computing, networking, and signal processing. However, it is widely accepted that a radical paradigm shift from purely CMOS technology to hybrid CMOS/nanodevice circuits is essential to achieve such level of miniaturization. We propose to work on a particular circuit concept, dubbed CMOL, for which the application prospects look best. Such a circuit would combine a level of advanced CMOS fabricated by the usual lithographic patterning, and a nanodevices which are formed (e.g., self-assembled) at each crosspoint of a "crossbar" array, consisting of two levels of nanowires fabricated by an advanced patterning technique, such as nanoimprint or EUV interference lithography which have good prospects for the half-pitch reduction to 3 nm or so within the next decade. The crucial element of hybrid design is the interface between CMOS and nanodevices. In the CMOL circuits the interface will provided by pins that are distributed all over the circuit area, on the top of the CMOS stack. Silicon-based technology necessary for fabrication of pins with nanometer-scale tips has been already developed in the context of field-emission arrays.

* information listed above is at the time of submission.

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