Frequency-Domain GPS Software Radio Receiver and Prototype

Award Information
Agency:
Department of Defense
Amount:
$99,993.00
Program:
SBIR
Contract:
FA9300-04-M-1014
Solitcitation Year:
2004
Solicitation Number:
2004.1
Branch:
Air Force
Award Year:
2004
Phase:
Phase I
Agency Tracking Number:
F041-296-1589
Solicitation Topic Code:
AF04-296
Small Business Information
SIGTEM TECHNOLOGY, INC.
113 Clover Hill Lane, Harleysville, PA, 19438
Hubzone Owned:
N
Woman Owned:
N
Socially and Economically Disadvantaged:
N
Duns:
869012732
Principal Investigator
 Chun Yang
 Principal Scientist
 (215) 513-9477
 chunyang@sigtem.com
Business Contact
 Chun Yang
Title: President
Phone: (215) 513-9477
Email: chunyang@sigtem.com
Research Institution
N/A
Abstract
We propose to develop a frequency-domain GPS software radio receiver based on our patented architecture and algorithms with real-time FPGA implementation. The frequency-domain approach directly manipulates GPS signal and correlation spectra to achieve the joint estimation of code phase, carrier phase and frequency, and other parameters. It is based on the concept of delay-Doppler mapping of complex correlations, equivalent to sampling the GPS signal's complex ambiguity function. It thus allows for fast parallel search in time and frequency dimensions and applies iterative processing with multiresolution in time, frequency, and signal quantization, essential for monitoring signal quality (anomalies) and mitigating environmental effects (multipath, interference, and near-far problems). To perform domain conversions for wideband signals in large blocks, we propose an innovative bitwise FFT algorithm by eliminating all time-consuming resource-demanding complex multiplications and only keeping simple and easy additions, thus making it suitable for real-time hardware implementation. In Phase I, the proposed system concept will be refined with the enabling algorithms developed. We will perform a preliminary hardware design and characterize the algorithms by means of analysis and numerical simulation. In Phase II, the recommended architecture and the validated algorithms will be implemented in a breadboard prototype for demonstration.

* information listed above is at the time of submission.

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