Deep Submicron Radiation Hardened Logic for Communications
Small Business Information
SILICON SPACE TECHNOLOGY CORP.
804 Las Cimas Parkway, Suite 140, Austin, TX, 78746
AbstractSilicon Space Technology (SST), working with Texas Instruments (TI), proposes to simulate, develop and demonstrate a method for radiation-hardening of TI-_s 65nm C021 process with SST-_s Buried Guard Ring (BGR) innovation. The finite width of the vulnerable region during a particle strike presents the greatest single challenge to deep submicron scaling. The width of the charge track alone is on the order of a micron. Subsequent response of the parasitic bipolar junctions can typically increase this vulnerable region by several microns. This spreading thwarts any spatial redundancy schemes such as triple module redundancy or DICE when the redundant parts become too close-as will typically happen at 65nm. Adding BGR to the C021 process will limit the secondary response of the junctions to a strike, thus limiting approximately the vulnerable region to the original charge track. A dual interlocked cell, DICE, will be designed in the C021 process to survive such strikes, partly by taking advantage of the BGR. A version of the DICE cell will also be designed to survive grazing angle strikes which can strike two sensitive node pairs simultaneously. BENEFIT: Silicon Space Technology is developing and demonstrating multiple radiation-hardened client-based processes and products in a commercial foundry manufacturing environment through integration of our unique RH process modules "C which have been proven in silicon products. SST-_s techniques are both patented and have other patents pending. SST-_s BGR and PID technology mitigate Single-Event Effects (SEE) by significantly reducing the cross-section. BGR significantly increases Dose Rate (DR) threshold performance to > 6.8E9 rad(Si)/sec, and PID can be tailored to increase Total Ionizing Dose (TID) performance beyond the Mrad level. The Company will use both government R&D and venture capital funding to further establish its RH technology at a commercial IC foundry to pervade the Space/Mil/Aero electronics marketplace using the fabless -oRH Client Process- model. Our multi-faceted fabless business/technical strategy is in its fifth year of commercialization, and we have been advised our innovations have progressed rapidly to a TRL = -Y6. SST-_s strategic competitive advantages spring from the ability to redesign any commercial semiconductor manufacturing process by adding unique RH process modules which transform the commercial process into a new radiation-hardened process variant. Additional advantages can be gained by providing a streamlined approach toward translating circuit designs from the original commercial process to the new radiation-hardened version of that process-as is proposed here using TI-_s commercial 65nm C021 process. The SST model is similar to the proven fabless IC production model invoked by many successful IC design companies throughout the world, but employs the unique -oRH Client Process- "C IP which provides the Company with a strategically significant advantage. By partnering with the USA-based third-largest semiconductor company in the world, who produces thousands of leading-edge standard products for commercial markets, a broad selection of domestically-produced, high-reliability parts could be made available to supply demanding industrial semiconductor markets. Our first objective, which completed fabrication in 2005 and radiation testing in 2006, was to integrate HBI-_s BGR and PID alternatives into multiple commercial processes to demonstrate effectiveness for seamless integration, radiation hardness, and portability of the concepts. Now also proven in a 180nm 16Mb SRAM product, SST is positioned to begin moving forward with commercialization and productization at several technology nodes. SST engaged with Texas Instruments (TI) in 2006 and has now integrated both BGR and PID modules into multiple TI CMOS processes (e.g., 250nm, 180nm, 130nm). The Company will be applying the same methodology as we move into 90nm and 65nm for future products. SST is negotiating a Foundry Services Agreement with TI for manufacture of SST-_s first memory product in 2008, the RH 16Mb monolithic SRAM, along with other SST memory products currently being designed. This agreement enables a domestic manufacturing source for SST-_s 180nm SRAM business now and, in combination with a License Agreement also under negotiation, enables TI-_s incorporation of SST RH IP in existing commercial products "C providing both companies with a path to scale future RH IC products to 65nm. These agreements enable SST and TI to leverage HBI Technology in various CMOS processes to provide a variety of products for various applications throughout the broad spectrum of industrial semiconductor markets. SST is currently creating demand for its technology by working closely with several prospective aerospace and defense contractors in the Space/Mil/Aero market segment. These contractors, who already utilize older generation radiation-hardened IC products, have a fundamental need for new leading-edge enhanced RH IC products. During the next 3-4 years, SST expects to generate revenues from five sources: 1) Department of Defense (DOD) R&D contracts; 2) non-recurring engineering (NRE) services related to integration of its IP into customer IC-_s and manufacturing support at commercial IC foundries; 3) licenses to use SST-developed HBI IP and RH cell libraries to manufacture custom circuits; 4) royalties received from all IC-_s sold containing HBI IP; and 5) radiation-hardened SRAM sales. During 2008-2009, the company expects a majority of revenues will be derived almost exclusively from DOD investments, NRE services and licensing. The Company-_s strategy is to introduce its proprietary RH technology first into the critical-need Space/Mil/Aero SRAM market using the fabless manufacturing business model with our foundry supplier "C Texas Instruments. Propelled by our -oRH Client Process- capability and the manufacturing prowess of commercial foundries, the Company fully expects to become the de-facto standard for next-generation circuits in the broader high-reliability marketplace. Further proliferation, via technology licensing opportunities and HiRel variants of TI-_s commercial products, is envisioned in the low-power implanted medical device market and other high-reliability industrial IC markets. The worldwide space electronics market is approximately $1.7 billion annually, with roughly 70% of this market requiring radiation-tolerant and harder components. Roughly 50% of this market is U.S. based, while an additional 16% of this remaining market is within countries that do not preclude export (ITAR) or do not have competition barriers that would limit successful export of the product. The total addressable market for our solution is approximately $850M "C with ASIC-_s comprising ~28% and memory ~22%. The establishment of each foundry -oRH Client Process- technology node will require ~$5-12M for qualification.
* information listed above is at the time of submission.