Space Qualified SDRAM Memory

Award Information
Agency:
Department of Defense
Branch
Air Force
Amount:
$738,953.00
Award Year:
2009
Program:
SBIR
Phase:
Phase II
Contract:
FA9453-09-C-0029
Award Id:
86706
Agency Tracking Number:
F073-097-0394
Solicitation Year:
n/a
Solicitation Topic Code:
n/a
Solicitation Number:
n/a
Small Business Information
3620 Lost Creek Boulevard, Austin, TX, 78735
Hubzone Owned:
N
Minority Owned:
N
Woman Owned:
N
Duns:
147671957
Principal Investigator:
David Gifford
Principal Engineer
(512) 989-9719
dgifford@siliconspacetech.com
Business Contact:
Jon Gwin
Vice President
(210) 822-9706
jgwin@siliconspacetech.com
Research Institution:
n/a
Abstract
Silicon Space Technology, working with Texas Instruments (TI), proposes to demonstrate an innovative radiation-hardened (RH) high-density SDRAM by adding proprietary Hardened-by-Process (HBP) modules plus a simple capacitor structure to TIs baseline 130nm process. HBP enables production of radiation-hardened integrated circuits at leading-edge circuit densities within any commercial silicon foundry, for use in both terrestrial and space systems. These methods do not adversely affect either circuit performance or yield. SST has demonstrated HBP as a solution to the major space radiation effects Single-Event Effects (SEE), Total Ionizing Dose (TID) & Dose Rate (DR) producing RH IEEE-1394B PHY and 16 Mb SRAM devices. Radiation testing of these devices has shown SSTs HBP approach significantly improves SEE performance (e.g., SEL, SET, & SEU), DR and has shown complete TID immunity to > 1Mrad(Si). The capacitor will be based on structures previously used by mainstream DRAM manufacturers and will be produced using a modular add-in into TIs baseline process. Although Phase II funding is not adequate to produce this device, we will design and simulate the circuit to prove its viability. This will enable manufacture of RH DRAMs 4x denser than currently available and will demonstrate the feasibility of future (higher-density) devices. BENEFITS: The first product design on the 130nm RH SDRAM process would be a 64Mb single data rate SDRAM. This chip would of similar size as our current 180nm 16Mb SRAM, but with four times the density. The exact configuration of the SDRAM would be determined based on customer input. This is a large enough SDRAM to gain market acceptance and, based on estimated cell size and TIs world class defectivity, should be manufacturable in TIs US factories. Depending on the success of this product, other offerings such as double data rate and larger density memories could be made available. The total dose hardness of the RH DRAM, based on recent results from the 180nm process, is expected to be about 300 krad(Si). Dose Rate and SEU performance is expected to be similar to the 16Mb SRAM.

* information listed above is at the time of submission.

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