SOI MESFETs for Ultra-Low Power Electronic Circuits

Award Information
Agency:
Department of Defense
Branch
Defense Advanced Research Projects Agency
Amount:
$98,975.00
Award Year:
2007
Program:
STTR
Phase:
Phase I
Contract:
W31P4Q-07-C-0256
Award Id:
83215
Agency Tracking Number:
07ST1-0083
Solicitation Year:
n/a
Solicitation Topic Code:
n/a
Solicitation Number:
n/a
Small Business Information
16411 N SKYRIDGE LN, FOUNTAIN HILLS, AZ, 85268
Hubzone Owned:
N
Minority Owned:
N
Woman Owned:
N
Duns:
185307266
Principal Investigator:
JOSEPHERVIN
CHIEF TECHNICAL OFFICER
(480) 298-1847
jervin@sjtmicropower.com
Business Contact:
PAMELADISALVO
BUSINESS ADMINISTRATOR
(480) 816-8077
pdisalvo@sjtmicropower.com
Research Institute:
ARIZONA STATE UNIV.
Dudley Sharp
ORSPA
Adm-B Wing 163, PO BOX 873505
TEMPE, AZ, 85287-3503
(480) 965-0273
Nonprofit college or university
Abstract
Simulations of high performance silicon-on-insulator (SOI) MESFETs show that they can be used for ultra-low power (ULP) radio frequency electronics with power added efficiencies (PAE) that are 10 times higher than existing solutions. The high PAE comes from the enhanced voltage swing that the MESFETs can tolerate (5-50V) compared to current VLSI CMOS technologies (1-5V). The SOI MESFETs can be fabricated economically using existing SOI CMOS foundries with no changes to the CMOS process flow. This means the SOI MESFETs can be integrated with state-of-the-art CMOS for ULP mixed signal circuit applications, something that is impossible with GaAs based devices. We propose to design an SOI MESFET based Class E amplifier for ULP communications applications in the Industrial-Scientific-Medical band of frequencies. The MESFET based designs will be compared to equivalent CMOS circuits to quantify the anticipated improvement in the PAE of the MESFET circuits. A hardware demonstrator of the Class E amplifier will be designed and tested using existing SOI MESFETs from a previous SBIR contract. Other examples of ULP circuits in which inductive loads lead to device voltages that would cause failure in traditional CMOS will be explored in any Phase II activity.

* information listed above is at the time of submission.

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