SBIR Phase I: Optical Motherboards with Nano-Second Memory Bus Latency enabled by CMOS-Compatible Inter-Chip Optical Communications Platform

Award Information
Agency:
National Science Foundation
Branch
n/a
Amount:
$100,000.00
Award Year:
2007
Program:
SBIR
Phase:
Phase I
Contract:
0637779
Award Id:
84628
Agency Tracking Number:
0637779
Solicitation Year:
n/a
Solicitation Topic Code:
n/a
Solicitation Number:
n/a
Small Business Information
201 CIRCLE DRIVE NORTH, SUITE 102/103, PISCATAWAY, NJ, 08854
Hubzone Owned:
N
Minority Owned:
N
Woman Owned:
N
Duns:
787144807
Principal Investigator:
JieYao
DPhil
(732) 885-5909
jyao@structuredmaterials.com
Business Contact:
JieYao
DPhil
(732) 885-5909
jyao@structuredmaterials.com
Research Institute:
n/a
Abstract
This Small Business Innovation Research (SBIR) Phase I project will result in a computer bus system with nanosecond latency time in addition to enhanced bus bandwidth. The rapid growth in computer speed is fueled by the increasing device density and computing speeds. However, a major roadblock to fully realizing the increasing computer power has been the inability to increase inter-chip communication speeds, the inter-chip latency time has remained constant at about 30ns for the past decade. The dominant performance limiting factor in modern computing has become the long latency time associated with the mother board data bus connecting the fast CPU and memory chips. As a result, with the increasing gap between the ever-increasing fast CPU and memory chip speeds and the slow mother board data bus speeds, data transfer has become the dominant performance limiting factor. Many important high-end applications today are extremely sensitive to memory access performance. As a way to alleviate the slow bus problem, computer architecture designers today are forced to develop more and more complex memory subsystems, such as adding hierarchical cache levels and designing complicated pre-fetching mechanisms, sacrificing chip size, performance and cost. Relying on the speed of light, which is not encumbered (slowed down) by electrical capacitances and resistances, this inter-chip optical bus platform will significantly reduce present memory bus latency (communication speed) from around 30 nano-seconds by at least a factor of 30 to 1nano-second, thus removing the memory access bottleneck.

* information listed above is at the time of submission.

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