SEU/SEL Resistant Ultra-Low Power Asynchronous Processor Design for Low-Temperature Applications

Award Information
Agency:
National Aeronautics and Space Administration
Branch
n/a
Amount:
$99,992.00
Award Year:
2009
Program:
SBIR
Phase:
Phase I
Contract:
NNX09CD75P
Award Id:
90674
Agency Tracking Number:
085270
Solicitation Year:
n/a
Solicitation Topic Code:
n/a
Solicitation Number:
n/a
Small Business Information
700 West Research Center Blvd, Fayetteville, AR, 72701
Hubzone Owned:
N
Minority Owned:
N
Woman Owned:
N
Duns:
044870363
Principal Investigator:
Matthew Leftwich
Principal Investigator
(479) 856-6367
mleftwich@spacephotonics.com
Business Contact:
Matthew Leftwich
PI/COO/Sr. Systems Engineer
(479) 856-6367
mleftwich@spacephotonics.com
Research Institution:
n/a
Abstract
This Phase I SBIR proposal seeks funding to develop a radiation-hardened circuit architecture to achieve SEU and SEL immunity by using delay-insensitive asynchronous logic, and to demonstrate its feasibility, effectiveness, and efficiency. Further, early studies reveal that an operational temperature range of 2K to 400K will be highly feasible. Delay-insensitive asynchronous logic removes the concept of a global clock by incorporating handshaking protocols to control the circuit. The handshaking protocols allows for flexible timing requirements, high power efficiency, and low noise/emission generation. The flexible timing nature of delay-insensitive logic makes this type of circuits an excellent candidate for mitigating radiation effects in digital electronics. Compared to the existing radiation-hardening techniques, the proposed solution has several substantial benefits including cost efficiency, SEU/SEL immunity without weak points, and the ability to retain data during power cycling while mitigating SEL. In addition, significantly improved supply voltage variation sustainability and security against power-based side-channel attacks can also be achieved.

* information listed above is at the time of submission.

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