MICROELECTRONIC INFORMATION PROCESSING SYSTEMS.

Award Information
Agency:
National Science Foundation
Branch
n/a
Amount:
$49,000.00
Award Year:
1988
Program:
SBIR
Phase:
Phase I
Contract:
n/a
Agency Tracking Number:
7586
Solicitation Year:
n/a
Solicitation Topic Code:
n/a
Solicitation Number:
n/a
Small Business Information
Space Tech Corpon
2324 Manchester Court, Fort Collins, CO, 80526
Hubzone Owned:
N
Socially and Economically Disadvantaged:
N
Woman Owned:
N
Duns:
n/a
Principal Investigator:
DR MICHANDREWS
() -
Business Contact:
() -
Research Institution:
n/a
Abstract
EXPLORATORY RESEARCH IS PROPOSED TO DETERMINE THE IMPLEMENTATION FACTORS PARAMETERS FOR A NEW VLSI CELL INVOKING REDUNDANT NUMBER ARITHMETIC INSTEAD OF 1'S/2'S COMPLEMENT. A NARROW APPLICATION TOWARDS SIGNAL PROCESSING (MULTIPLY/ACCUMULATE INTENSIVE) SHALL DRIVE MINIMAL AREA AND SPEED DESIGNS. CARRY/BORROW FREE DESIGNS MAY GREATLY ENHANCE MODULAR FAULT-TOLERANT IMPLEMENTATIONS. FOR FURTHER FOCUS, THE EFFICIENT SIGNED BINARY NUMBER REPRESENTATION (SBNR) AS A TRIT-VALUED SUBSET OF GENERAL REDUNDANT NUMBER REPRESENTATIONS AFFORDS MORE IMPROVED AREA/SPEED FOM'S, THUS MAKING SUCH CELLS HIGHLY VLSI-REGULAR. THIS APPLICATION SPECIFIC STUDY SHALL IDENTIFY CRITICAL DESIGN PARAMETERS (MINIMAL LINE WIDTHS, FUNCTIONAL PARTITIONING, VIA'S # OF GATES, INTER/INTRACELL CONNECTIONS) TO AID THE DESIGN ENGINEER. FOCUS IS ON LOWER LEVELS OF COMPUTER ARCHITECTURE COUPLED TO TECHNOLOGY/IMPLEMENTATION ISSUES WHERE SIGNIFICANT DISCOVERIES MAY BE LEVERAGED INTO PRACTICAL SYSTOLIC ARRAYS EXCEEDING THE DESIGN PERFORMANCE OF GAPP AND DAP DEVICES WHILE ACHIEVING BREAKTHROUGHS IN MINIMAL CELL LAYOUTS.

* information listed above is at the time of submission.

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