COMPLEX INTEGRATED CIRCUIT TECHNOLOGY - THERMAL MANAGEMENT MATERIALS

Award Information
Agency:
Department of Defense
Branch
Air Force
Amount:
$57,421.00
Award Year:
1989
Program:
SBIR
Phase:
Phase I
Contract:
n/a
Award Id:
10194
Agency Tracking Number:
10194
Solicitation Year:
n/a
Solicitation Topic Code:
n/a
Solicitation Number:
n/a
Small Business Information
1104 Camino Del Mar, Del Mar, CA, 92014
Hubzone Owned:
N
Minority Owned:
N
Woman Owned:
N
Duns:
n/a
Principal Investigator:
John J Glatz
(619) 454-1133
Business Contact:
() -
Research Institution:
n/a
Abstract
SPARTA, INC. PROPOSES A PROGRAM TO ASSESS THE FEASIBILITY AND IMPLICATIONS OF USING ULTRA-HIGH THERMAL CONDUCTIVITY PITCH FIBERS (HIGH K) IN THE DISSIPATION OF VERY HIGH HEAT FLUXES GENERATED BY ADVANCED MICROCIRCUITS. THERE ARE THREE INNOVATIVE CONCEPTS TO THIS STUDY. FIRST, A SYSTEMS APPROACH WILL BE TAKEN TO ANALYZE THE PACKAGING REQUIREMENT (ELECTRICAL, THERMAL CONDUCTIVITY, DIELECTRIC CONSTANT) AND TRANSLATE THEM INTO MATERIAL PROPERTY GOALS. SECOND, GRAPHITE FIBER REINFORCED CERAMIC MATRIX COMPOSITES (CMC) AND GRAPHITE FIBER REINFORCED METAL MATRIX COMPOSITES (MMC) WITH CERAMIC COATINGS WILL BE CONSIDERED FOR MICROELECTRONIC PACKAGES MATERIALS. THIRD, MANUFACTURING FEASIBILITY STUDIES AND PROTOTYPE FABRICATION WILL BE CARRIED OUT TO ASSESS FABRICABILITY OF THESE NEW PACKAGING CONCEPTS. CMC AND MMC REINFORCED WITH HIGH K FIBER ARE IDEAL FOR THERMAL MANAGEMENT OF HIGH HEAT FLUX DEVICES. PACKAGES MADE FROM THIS MATERIAL WILL POSSESS VERY HIGH THERMAL CONDUCTIVITY (\400 W/M DEG C), LOW CTE (\C-4 PPM/DEG F) AND LOW DIELECTRIC CONSTANTS. FURTHERMORE, THE THERMAL CYCLING FATIGUE LIFE OF THE PACKAGE WILL BE EXTENDED DUE TO REDUCED CTE MIS-MATCH BETWEEN PACKAGE AND SUBSTRATE, AND REDUCED THERMAL GRADUENTS WITHIN THE PACKAGE. THE PROGRAM WILL CONSIST OF THE FOLLOWING BASIS: 1) IDENTIFICATION OF CANDIDATE COMPONENTS, 2) IDENTIFICATION OF CANDIDATE MATERIALS, 3) PARAMETRIC DESIGN ANALYSIS, 4) COMPOSITE MATERIAL CHIP CARRIER FABRICATION, 5) CERAMIC COATING OF CHIP CARRIER SPECIMEN, 6) DEPOSITION OF SILICON SUBSTRATE ON CERAMIC CHIP SURFACE, AND 7) TECHNOLOGY DEVELOPMENT PLAN.

* information listed above is at the time of submission.

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