MULTIPLE ION IMPLANTATION OF BURIED LAYERS FOR SILICON-ON-INSULATOR

Award Information
Agency:
Department of Defense
Branch
Missile Defense Agency
Amount:
$300,000.00
Award Year:
1989
Program:
SBIR
Phase:
Phase II
Contract:
n/a
Agency Tracking Number:
6478
Solicitation Year:
n/a
Solicitation Topic Code:
n/a
Solicitation Number:
n/a
Small Business Information
Spire Corp.
Patriots Pk, Bedford, MA, 01730
Hubzone Owned:
N
Socially and Economically Disadvantaged:
N
Woman Owned:
N
Duns:
n/a
Principal Investigator:
Stephen N Bunker
(617) 275-6000
Business Contact:
() -
Research Institution:
n/a
Abstract
FABRICATING SILICON-ON-INSULATOR (SOI) SUBSTRATE IS A SUBJECT OF KEEN INTEREST BECAUSE OF THE WIDE VARIETY OF MAJOR ELECTRICAL BENEFITS THATCAN BE OBTAINED FOR INTEGRATED CIRCUITS. THE MOST PROMISING TECHNOLOGY IS ION IMPLANTATION OF BURIED LAYERS BECAUSE OF PROCESS CONTROLLABILITY, MILD DEFECTS, AND LARGE AREA UNIFORMITY. COMPLEX DEVICE FABRICATION HAS BEEN SUCCESSFULLY DEMONSTRATED. THE IMPLANTATION TECHNIQUE LENDS ITSELF TO A VARIETY OF NOVEL PROCESS MODIFICATIONS TO ENHANCE THE PERFORMANCE OF THE BASIC SOI MATERIAL. METHODS ARE BEING INVESTIGATED FOR CREATING MUCH HIGHER VOLTAGE ISOLATION THAN NORMALLY AVAILABLE AND SIGNIFICANTLY DECREASED PARASITIC CAPACITANCE. A UNIQUE MULTIPLE ION IMPLANT PROCESS IS BEINGUSED TO FABRICATE THE MATERIAL. THE SILICON-ON-INSULATOR SUBSTRATES BEING FABRICATED ARE ESPECIALLY USEFUL FOR MIXING VERY HIGH VOLTAGE CIRCUIT ELEMENTS WITH CONTROL STRUCTURES. THIS IS IMPORTANT FOR RADIATION-HARD POWER CONTROL DEVICES. THE DECREASED PARASITC CAPACITANCE GEOMETRY IS IMPORTANT FOR INCREASING DEVICE SPEED, DECREASING GATE THRESHOLD SENSITIVITY TO SUBSTRATE BIAS, AND CORRECTING THE KINK FREQUENTLY OBSERVED IN THE CHARACTERISTIC DEVICE CURVES.

* information listed above is at the time of submission.

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