BUILT-IN TEST (BIT) APPROACHES FOR END-TO-END TESTABILITY OF RF CIRCUITS

THE COMPLEXITY AND HIGH DENSITY OF STATE-OF-THE-ART RF EQUIPMENT IS CREATING AN INCREASED NEED FOR BIT TECHNOLOGY. TEST POINTS ARE MORE DIFFICULT TO ACCESS IN MODERN INTEGRATED RF CIRCUITS AND MAINTAINING A COMPLETE INVENTORY OF RF TEST EQUIPMENT IS BECOMING MORE DIFFICULT AND EXPENSIVE. THE COMPLEXITY OF RF CIRUITRY IS INCREASING THE NECESSARY SKILL LEVEL OF TECHNICANS NEEDED TO DIAGNOSE AND REPAIR HARDWARE FAILURES. NEW AND INNOVATIVE BIT MECHANISMS DESIGNED SPECIFICALLY FOR RF HARDWARE ARE NEEDED TO PROVIDE THE COST EFFECTIVE AND REAL-TIME DETECTION, ISOLATION, AND DIAGNOSIS OF RF CIRCUIT FAILURES. SRS PROPOSES TO DEVELOP END-TO-END BIT TECHNIQUES WHICH WHEN COMBINED PROVIDE NEAR ONE HUNDRED PERCENT FAILURE COVERAGE IN RF CIRCUITS AND EQUIPMENT. SRS'S APPROACH IS BASED ON STIMULATING THE RF CIRCUITS WITH PREFORMATTED TEST PATTERNS WHILE SAMPLING CIRCUIT RESPONSES FROM TEST POINTS AND SENSING INTERFACES TO COMPARE THEM TO STORED SAMPLES OF NOMINAL CIRCUIT RESPONSES. THE EFFORT WILL LEAD TO THE CONCEPTUAL DESIGN OF INTEGRATED END-TO-END BIT METHODS FOR IMPLEMENTATION IN ACTUAL RF HARDWARE IN PHASE II.