GAAS RISC ARRAY PROCESSOR

Award Information
Agency:
National Aeronautics and Space Administration
Branch
n/a
Amount:
$497,972.00
Award Year:
1989
Program:
SBIR
Phase:
Phase II
Contract:
n/a
Agency Tracking Number:
8191
Solicitation Year:
n/a
Solicitation Topic Code:
n/a
Solicitation Number:
n/a
Small Business Information
Systems & Processes Engineerin
1406 Smith Road Suite A, Austin, TX, 78721
Hubzone Owned:
N
Socially and Economically Disadvantaged:
N
Woman Owned:
N
Duns:
n/a
Principal Investigator:
Dr Gary B Mcmillian
() -
Business Contact:
() -
Research Institution:
n/a
Abstract
SYSTEMS & PROCESSES ENGINEERING CORPORATION (SPEC) HAS DEVELOPED AN INNOVATIVE ARRAY PROCESSOR ARCHITECTURE FOR COMPU- TING FOURIER TRANSFORMS AND OTHER COMMONLY USED SIGNAL PROCESSING ALGORITHMS. THIS ARCHITECTURE IS DESIGNED TO EX-TRACT THE HIGHEST POSSIBLE ARRAY PERFORMANCE FROM STATE-OF- THE-ART GAAS TECHNOLOGY. THE ARCHITECTURAL DESIGN FEATURES A HIGH PERFORMANCE RISC PROCESSOR IMPLEMENTED IN GAAS, ALONGALONG WITH A FLOATING POINT COPROCESSOR AND A UNIQUE ARRAY COMMUNICATIONS COPROCESSOR, ALSO IMPLEMENTED IN GAAS. THE ARCHITECTURE INCLUDES VERY HIGH SPEED, LOW GATE COUNT BIT-SERIAL ARITHMETIC AND COMMUNICATION UNITS IN THE FLOAT- ING POINT AND COMMUNICATION COPROCESSORS, RESPECTIVELY. UTILIZING THE VERY HIGH SPEED OF GAAS, CURRENTLY WITH CLOCK RATES IN EXCESS OF 1 GHZ, BIT-SERIAL UNITS CAN BE USEDTO FORM THE CORE OF COMPLEX ARITHMETIC AND COMMUNICATIONS UNITS. A BIT-SERIAL VLSI ARCHITECTURE IS, IN FACT, IDEAL FORIMPLEMENTATION OF THE COMMUNICATION LINKS BETWEEN PROCESSORSTHE OBJECTIVE OF THE PHASE II PROGRAM IS TO DESIGN AND SIMU-LATE AN ARRAY PROCESSOR UTILIZING HIGH PERFORMANCE GAAS RISCPROCESSORS AND COPROCESSORS.

* information listed above is at the time of submission.

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