GSAS DATAPATH COMPILATION

Award Information
Agency:
Department of Defense
Branch
Defense Advanced Research Projects Agency
Amount:
$50,000.00
Award Year:
1990
Program:
SBIR
Phase:
Phase I
Contract:
n/a
Award Id:
13527
Agency Tracking Number:
13527
Solicitation Year:
n/a
Solicitation Topic Code:
n/a
Solicitation Number:
n/a
Small Business Information
1406 Smith Rd, Austin, TX, 78721
Hubzone Owned:
N
Minority Owned:
N
Woman Owned:
N
Duns:
n/a
Principal Investigator:
Dr Gary Mcmillian
(512) 385-0082
Business Contact:
() -
Research Institution:
n/a
Abstract
SYSTEMS & PROCESSES ENGINEERING CORPORATION (SPEC) HAS DEVELOPED A PROGRAM TO DEMONSTRATE TECHNOLOGY INDEPENDENT COMPILER TECHNOLOGY. SPEC HAS A JOINT DEVELOPMENT AGREEMENT WITH VLSI TECHNOLOGY AND WITH VITESSE SEMICONDUCTOR TO DEVELOP GAAS DATAPATH "LEAF CELLS" FOR USE WITH VLSI TECHNOLOGY'S DATAPATH COMPILER. THE DATAPATH COMPILER USES TECHNOLOGY SPECIFIC LEAF CELLS TO CONSTRUCT OPTIMIZED N-BI DATAPATHS FROM TECHNOLOGY INDEPENDENT SCHEMATIC DESIGNS. THE COMPILED LYAOUT OFFERS HIGHER PERFORMANCE,LOWER POWERAND SMALLER SIZE THAN STANDARD CELL OR GATE ARRAY BASED DESIGNS. INITIAL DEVELOPMENT WILL BE FOR VITESSE'S DIRECT COUPLED FET LOGIC (DCFL) ENHANCEMENT/DEPLETION MODE GAAS PROCESS. DCFL CAN BE USED TO DESIGN HIGH SPEED, LOW POWER GAAS LOGIC, AND INTEGRATION LEVELS ARE PROJECTED TO REACH 100K EQUIVALENT NOR GATES BY THE END OF 1990. A BASIC SET OF DCFL ELEMENT CELLS WILL BE DEVELOPED (E.G. ALU, BARREL SHIFTER, REGISTER FILE, ADDER, MULTIPLEXOR, FLIP-FLOP, LATCH). DEVELOPMENT OF SOURCE COUPLED FET LOGIC (SCFL) LEAF CELLS WILL BE INVESTIGATED FOR APPLICATIONS THAT REQUIRE VERY HIGH SPEED GAAS DATAPATH LOGIC. SCFL OFFERS HIGHER SPEED AT THE EXPENSE OF INCREASED POWER COMSUMPTION AND LARGER LEAF CELLS. ANTICIPATED BENEFITS/POTENTIAL COMMERCIAL APPLICATIONS - DEVELOPMENT OF GAAS DATAPATH LEAF CELLS WILL ENABLE INTEGRATED CIRCUIT DESIGNERS TO IMPLEMENT DESIGNS IN EITHER CMOS OR GAAS, AFTER COMPLETION OF THE FUNCTIONAL DESIGN. UPON COMPLETION OF THIS PROGRAM, FUNCTIONAL LEVEL ASIC DESIGNS CAN BE TRANSPARENTLY IMPLEMENTED IN GAAS OR CMOS, AS REQUIRED TO ACHIEVE OPTIMIXAED SYSTEM PERFORMANCE, E.G. HIGHER PERFORMANCE OR LOWER POWER COMSUPMTION. KEY WORDS - GALLIUM ARSENIDE, GAAS, DATAPATH COMPILER, LOGIC SYNTHESIS, CAE.

* information listed above is at the time of submission.

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