Reconfigurable Processors for Software Protection
Small Business Information
SYSTRAN FEDERAL CORP.
4027 Colonel Glenn Highway, Suite 210, Dayton, OH, 45431
AbstractSystran Federal Corporation is proposing to solve the software protection problem by developing a reconfigurable processor, in which the opcode instruction set could be changed. We are proposing the development of the tools and the mechanisms that arerequired for a reconfigurable processor with a variable opcode instruction set, to defeat any effort to reverse engineer the protected software. Each time source code is compiled targeting a system, the software tools, such as, the assembler used togenerate the executable code, should know the instruction set that is used in that particular system. When the Field Programmable Gate Array (FPGA) design tools are available the instruction set could be modified and a new instruction set incorporated tothe reconfigurable processor. The processor will be embedded in the FPGA such that the pins cannot be accessed using hardware.We are also proposing another method based on encrypting the executable code. In this method, we propose to encrypt the executable code that is targeted to be executed on the reconfigurable processor. The instruction set of the reconfigurable processorwould not be reprogrammable. However, the executable code is assumed to be encrypted using a set of keys of a known length. The instructions will be decrypted using the set of keys that is unique to each processor. The decryption module and the set of keysare embedded at design time in the FPGA and are not visible by software. The keys are assumed to be of adequate length such that it will require an enormous amount of time to do a comprehensive analysis when the decryption algorithm is known. Thedecryption module and the processor would be embedded in the FPGA such that the pins cannot be accessed using hardware. The main benefit of this effort would be that an executable program software could be protected from reverse engineering using a variable opcode instruction set reconfigurable processor.
* information listed above is at the time of submission.