THE USE OF ULTRA VIOLET RADIATION TO IMPROVE CHIPS USED IN NEURAL NETWORKS

Award Information
Agency:
National Science Foundation
Branch:
N/A
Amount:
$224,553.00
Award Year:
1991
Program:
SBIR
Phase:
Phase II
Contract:
N/A
Agency Tracking Number:
11869
Solicitation Year:
N/A
Solicitation Topic Code:
N/A
Solicitation Number:
N/A
Small Business Information
Tanner Research
444 North Altadena Dr, Pasadena, CA, 91107
Hubzone Owned:
N
Socially and Economically Disadvantaged:
N
Woman Owned:
N
Duns:
N/A
Principal Investigator
 Dr John E Tanner
 President
 () -
Business Contact
Phone: () -
Research Institution
N/A
Abstract
ANALOG QUANTITIES IN ON-CHIP LONG-TERM STORAGE CAN BE USED TO COMPENSATE FOR FABRICATION VARIATIONS AND TO PROVIDE VARIABLE SYNAPSES IN NEURAL NETWORKS. THE VOLTAGE ON FLOATING POLYSILICON GATES OF A STANDARD CMOS INTEGRATED CIRCUIT CAN BE SET BY SHINING UNIFORM ULTRAVIOLET LIGHT ON THE CHIP AND ARRANGING THE CIRCUIT TOPOLOGY AND GEOMETRY SO THAT NEARBY ACTIVE AREAS HAVE THE CORRECT VOLTAGES. THIS TECHNIQUE IS CURRENTLY UNDER INVESTIGATION FOR NULLING OUT OFFSET VOLTAGES OF AMPLIFIERS DUE TO TRANSISTOR MISMATCHES IN INTEGRATED CIRCUITS FABRICATED WITH ORDINARY CMOS PROCESSES. WE WILL CONTINUE THIS LINE OF RESEARCH AND ALSO INVESTIGATE THE USE OF A SIMILAR TECHNIQUE TO SET THE WEIGHT OF SYNAPSESIN A HOPFIELD STYLE NEURAL NETWORK. IF POSSIBLE, WE WILL USE THE INCREMENTAL NATURE OF THE UV-INDUCED CURRENT IN A LEARNING ALGORITHM. A BUILT IN LEARNING ALGORITHM WILL ALSO COMPENSATE FOR VARIATIONS IN NEURON AMPLIFIERS DUE TO FABRICATION IRREGULARITIES. OUR EXPERIMENTAL INVESTIGATION TECHNIQUE WILL RELY HEAVILY ON DESIGN, FABRICATION, AND TESTING OF SMALL INTEGRATED CIRCUITS. WE WILL FOCUS ON OVERCOMING CIRCUIT PROBLEMS AND PRODUCING WORKING LABORATORY PROTOTYPES. TEST CHIPS WILL BE FABRICATED THROUGH MOSIS.

* information listed above is at the time of submission.

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