HIGH-PERFORMANCE ANALOG CMOS CONVOLVER

Award Information
Agency:
National Science Foundation
Amount:
$64,937.00
Program:
SBIR
Contract:
N/A
Solitcitation Year:
N/A
Solicitation Number:
N/A
Branch:
N/A
Award Year:
1994
Phase:
Phase I
Agency Tracking Number:
27443
Solicitation Topic Code:
N/A
Small Business Information
Tanner Research Inc.
180 N Vinedo Ave, Pasadena, CA, 91107
Hubzone Owned:
N
Woman Owned:
N
Socially and Economically Disadvantaged:
N
Duns:
N/A
Principal Investigator
 Massimo A Sivilotti
 (818) 792-3000
Business Contact
Phone: () -
Research Institution
N/A
Abstract
RESEARCHERS ARE DESIGNING AND FABRICATING A HIGH-PERFORMANCE CONVOLVER INTEGRATED CIRCUIT, THAT CAN BE COUPLED TO A DIGITAL STOCHASTIC NEURAL NETWORK CLASSIFIER. THE ARCHITECTURE HAS A PREDICTED SINGLE-CHIP PERFORMANCE OF 50 BILLION MULTIPLY/ACCUMULATES PER SECOND. UNLIKE COMPETING NEURAL NETWORK INTEGRATED CIRCUITS, THIS THROUGHPUT CAN BE MAINTAINED WITH REALISTIC CHIP I/O BANDWIDTHS. THIS HIGH PERFORMANCE IS ACHIEVED AT THE ARCHITECTURE LEVEL BY EXPLOITING MASSIVE PARALLELISM IN COMPUTING SEVERAL CONVOLUTION KERNELS SIMULTANEOUSLY, AND AT THE CIRCUIT LEVEL BY USING COMPACT MULTIPLYING D/A CONVERTERS (MDACS) AND ANALOG CURRENT SUMMING. RESEARCHERS ARE DEVELOPING CUSTOM INTEGRATED CIRCUITS THAT SUPPORT THE CONSTRUCTION OF LARGE, HIGH PERFORMANCE NEURAL NETWORKS. THE EFFORT INCLUDES THE DESIGN AND FABRICATION OF A SMALL-SCALE PROTOTYPE CMOS INTEGRATED CIRCUIT TO PROVE THE FEASIBILITY OF THE DEVELOPMENT. THE APPROACH UTILIZES COMMERCIAL CMOS/BULK INTEGRATED CIRCUIT TECHNOLOGY. PRODUCTS ARISING FROM THIS R&D CAN BE FABRICATED RELIABLY AND ECONOMICALLY BY A NUMBER OF VENDORS.

* information listed above is at the time of submission.

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