Image Object Recognition Processor

Award Information
Agency:
Department of Defense
Branch
Navy
Amount:
$69,976.00
Award Year:
1994
Program:
SBIR
Phase:
Phase I
Contract:
n/a
Award Id:
26776
Agency Tracking Number:
26776
Solicitation Year:
n/a
Solicitation Topic Code:
n/a
Solicitation Number:
n/a
Small Business Information
180 North Vinedo Avenue, Pasadena, CA, 91107
Hubzone Owned:
N
Minority Owned:
N
Woman Owned:
N
Duns:
n/a
Principal Investigator:
Massimo Sivilotti
(818) 792-3000
Business Contact:
() -
Research Institution:
n/a
Abstract
We propose to design and fabricate a high-performance convolver integrated circuit, that can be coupled to a digital stochastic neural network classifier. Our architecture is optimized for image processing, and has a predicted single-chip performance of 50 billion multiply/accumulates per second. Unlike competing neural network integrated circuits, this throughput can be maintained with realistic chip I/O bandwidth. This high performance is achieved at the architecture level by exploiting massive parallelism in computing several convolution kernels simultaneously, and at the circuit level by using compact mulitplying D/A converters (MDACs) and analog current summing. We propose to research and develop custom integrated circuits that will support the construction of large, high performance neural networks. Our Phase I effort will include the design AND FABRICATION of a small-scale prototype CMOS integrated circuit to prove the feasibility of our development. Our approach will utilize commercial CMOS/bulk integrated circuit technology; products arising from this R&D can be fabricated reliably and economically by a number of vendors. We have previously demonstrated components for the core technology, and propose to augment the architecture with support for real-time, on-chip learning algorithms. The proposed research applies our expertise in mixed-signal design techniques and neural network architectures.

* information listed above is at the time of submission.

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