Airborne Sensor Front End Signal Processing Unit
Small Business Information
180 North Vinedo Avenue, Pasadena, CA, 91107
AbstractHigh resolution focal plane sensors typically exhibit significant pixel-to-pixel nonuniformities. These display artifacts are often larger than the minimum resolvable intensity variation in a single pixel, and consequently, limit the resolution of the system to a fraction of its potential. We propose to design an analog integrated circuit architecture that will perform 2-point (i.e., gain and offset) correction on a pixel by pixel basis. During the Phase I effort, we will design and manufacture prototype integrated circuits that will prove the concept. At this time, we anticipate that a complete system to correct a 256x256 sensor at 30 frames/sec will comprise 16 or fewer integrated circuits (with a total silicon die area of 10 cm ). Advanced integrated circuit fabrication processes could reduce this area to a single IC. Potential advantages over DSP solutions include: single chips solutions for 256x256 focal planes, ultra-low power consumption (less than 1mW), very high processing speed (10 Mpixels/sec per chip), scalable architectures to match any sensor configuration, and full analog processing for compatibility with existing sensor interfaces. The analog offset-gain corrector is compatible with an automatic gain control (AGC) circuit that matches the dynamic range of an image (up to 12 bits) with the reduced (8-bit) dynamic range of display/storage media.
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